Semiconductor Package with Varying Interconnection Layer Thickness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fan-out packaging, which offers high-density fine-pitch connections, faces higher conduction loss and signal distortion due to thinner interconnection lines, while Flip Chip Ball Grid Array (FCBGA) is thicker and less dense, compromising miniaturization and reliability.
Innovation Solution
A semiconductor device package design featuring a lower-density substrate with a higher-density substrate attached, incorporating interconnection layers and dielectric layers of varying thicknesses to manage signal transmission, with a thicker interconnection layer for high-speed data and thinner layers for lower data rates, reducing insertion loss and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If Fan-out packaging is used to achieve thin profile and high density fine-pitch connection, then package thickness is reduced and I/O pin density is increased, but conduction loss increases and signal distortion occurs
Solution Approach 1:
The patent applies different interconnection layer thicknesses at different locations within the same package structure. Specifically, the first interconnection layer has a first thickness while the second interconnection layer has a second thickness greater than the first thickness. This local differentiation allows thin interconnections in non-critical areas to achieve miniaturization while providing thicker interconnections in critical signal paths to reduce conduction loss and maintain signal integrity.
2Quantity of substance
If Fan-out packaging is used to achieve high density fine-pitch connection, then number of I/O pins is increased, but conduction loss increases due to thinner interconnection lines
Solution Approach 1:
The patent implements varying interconnection layer thicknesses to optimize the balance between I/O pin density and conduction loss. By making the second interconnection layer thicker than the first interconnection layer in specific regions, the design accommodates high-density fine-pitch connections where thin lines are acceptable while providing thicker conductors in paths where signal integrity is critical, thereby reducing overall conduction loss despite increased I/O pin count.
3Reliability
If Flip Chip Ball Grid Array is used to achieve lower conduction loss, then reliability is improved, but package thickness increases
Solution Approach 1:
The patent combines elements of both FCBGA and Fan-out packaging by implementing a hybrid structure with varying interconnection layer thicknesses. This allows the package to achieve thin overall profile characteristic of Fan-out packaging while incorporating thicker interconnection layers in specific regions to reduce conduction loss and improve signal integrity, thereby attaining reliability benefits of FCBGA without the thickness penalty.
Data Source
AI summary
A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.