Semiconductor Package Interconnects Reducing Parasitic Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in high-frequency applications due to large resistance components and significant cross-talk between wiring patterns in conventional semiconductor packages, and the through silicon via technology is difficult to form and results in reduced throughput and chip cracking.
Innovation Solution
A semiconductor package design that eliminates the need for through silicon via formation by using a redistribution layer and solder bumps to connect semiconductor dies, reducing parasitic capacitance and resistance, and utilizing a wafer-to-wafer or chip-to-wafer fabrication method to achieve low-cost and high-throughput production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon via technology is used to reduce resistance and parasitic capacitance, then electrical performance is improved, but manufacturing complexity and difficulty increase significantly
Solution Approach 1:
The patent extracts the through silicon via formation process from the manufacturing sequence and replaces it with an alternative approach using copper pillars and solder bumps formed directly on the chip surface. This eliminates the complex drilling, plugging, and electroplating steps required for through silicon vias while achieving similar electrical performance goals.
Solution Approach 2:
The patent uses temporary protective films and sacrificial layers during the copper pillar formation process that are removed or discarded in subsequent steps. This approach simplifies the overall manufacturing process compared to the permanent, complex through silicon via structure, allowing for easier and more cost-effective production.
2Reliability
If through silicon via formation process is implemented, then electrical performance improves, but production throughput decreases
Solution Approach 1:
The patent performs copper pillar formation and solder bump attachment as preliminary actions before final chip assembly. This allows these complex steps to be completed while the chip is still on the wafer or in a simplified state, increasing overall production throughput compared to performing through silicon via formation after chip fabrication is complete.
Solution Approach 2:
The patent segments the interconnection structure into separate components: copper pillars for electrical connection and solder bumps for mechanical attachment. This segmentation allows each component to be formed and optimized independently using simpler, faster processes rather than requiring the monolithic through silicon via structure.
3Reliability
If copper metal is filled into through silicon via, then electrical performance improves, but chip cracking occurs due to thermal expansion
Solution Approach 1:
The patent extracts the copper filling step from the through silicon via formation process and replaces it with copper pillar deposition on the chip surface. This eliminates the thermal expansion mismatch problem between copper and silicon that causes chip cracking, while still achieving low resistance electrical connections through the copper pillars and solder bumps.
Solution Approach 2:
The patent changes the physical state and positioning of the copper interconnection from being embedded deep within the silicon substrate (through silicon via) to being positioned on the chip surface (copper pillars). This parameter change in location and configuration eliminates the thermal stress concentration that leads to chip cracking during operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient signal transmission with reduced parasitic capacitance and resistance, facilitating high-frequency applications while maintaining low production costs and improving throughput by avoiding the complexities of through silicon via formation.
Implementation Method 1
a second solder bump coupled to the second redistribution layer and to the first solder bump
Data Source
AI summary
A semiconductor package includes a first semiconductor die; a first redistribution layer coupled to a bonding pad of the first semiconductor die; a first solder bump coupled to the first redistribution layer; a second semiconductor die; a second redistribution layer coupled to a bonding pad of the second semiconductor die; a second solder bump coupled to the second redistribution layer and to the first solder bump; a third redistribution layer coupled to the second redistribution layer; and a solder ball coupled to the third redistribution layer.