Semiconductor Package Interlink Blocks for Dense 3D Interconnects
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Solution Overview
Problem
The demand for size reduction and high-performance interconnecting elements in high-density integration packages is not adequately met by existing three-dimensional integration technologies for wafer level packaging.
Innovation Solution
The method involves forming interlink blocks with through insulation vias (TIVs) embedded in an encapsulant, where TIVs are metallic pillars with varying sizes and shapes, and a molding compound is used to encapsulate semiconductor dies and interlink blocks, allowing for efficient electrical connection and package integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional integration technology is used for wafer level packaging, then high-density integration is achieved, but size reduction and high-performance interconnecting elements are not adequately satisfied
Solution Approach 1:
The package structure is segmented into distinct functional regions: active dies, interlink blocks, and molding compound. The interlink blocks are further segmented into individual TIVs (through-insulator vias) that can be independently formed and tested. This segmentation allows for high-density integration while maintaining reliable, targeted interconnections through the TIVs that penetrate the molding compound to electrically connect different dies.
Solution Approach 2:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical integration by forming TIVs that extend through the molding compound in the vertical dimension. This enables interconnecting elements to pass through the package structure vertically, achieving high-density integration in the Z-direction while maintaining reliable electrical connections between multiple die layers.
2Volume of moving object
If size reduction is pursued in high-density integration packages, then compact packaging is achieved, but interconnecting element performance may be compromised
Solution Approach 1:
The TIVs are nested within the molding compound, with the conductive material embedded in the insulating molding material. This nested structure allows the interconnecting elements to be contained within the package volume without increasing external dimensions, achieving size reduction while maintaining reliable electrical connections through the embedded TIVs.
Solution Approach 2:
By utilizing the vertical dimension with TIVs extending through the molding compound thickness, the patent achieves compact horizontal packaging while maintaining reliable interconnections in the vertical direction. This dimensional transition enables small package footprint with robust three-dimensional interconnecting elements.
3Productivity
If known good TIVs are ensured through testing, then yield is improved, but additional process steps are required
Solution Approach 1:
The TIVs are formed and tested before final package assembly, allowing known-good interconnecting elements to be identified and selected in advance. This preliminary action of forming and testing TIVs separately enables yield improvement by ensuring only functional interconnects are used in the final package, while the modular approach manages process complexity.
Solution Approach 2:
The molding compound serves as an intermediary material that both encapsulates the TIVs and provides the insulating matrix for conductive interconnect formation. This intermediary structure enables integrated formation of insulator and conductor, simplifying the overall manufacturing process while allowing for testing and selection of known-good TIVs to improve yield.
Data Source
AI summary
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least includes a redistribution layer, a semiconductor die, an interlink block, and a molding compound. The semiconductor die is disposed on the redistribution layer, and the interlink block is disposed on the redistribution layer and beside the semiconductor die. The interlink block includes an insulating encapsulant and through insulator vias penetrating through the insulating encapsulant. The molding compound disposed on the redistribution layer laterally wraps around the semiconductor die and the interlink block. The interlink block is spaced apart from the semiconductor die with the molding compound there-between. The through insulator vias are isolated from the molding compound by the insulating encapsulant.