Semiconductor Package Interposer with Bridge Die and Through-Hole Frame
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Solution Overview
Problem
The miniaturization and multifunctionalization of electronic devices require effective interconnection of semiconductor chips, which existing semiconductor packages fail to guarantee due to inadequate interposer structures, leading to issues with chip connectivity and warpage characteristics.
Innovation Solution
A semiconductor package with a novel interposer structure featuring a frame with through-holes, bridge dies, encapsulants, and redistribution layers, utilizing organic material-based interposers with adjusted thicknesses to improve warpage characteristics and ensure reliable chip interconnection through conductive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing semiconductor package structures are used, then manufacturing is simpler, but chip interconnection reliability deteriorates
Solution Approach 1:
The interposer is divided into a frame structure with multiple through-holes, where each through-hole can accommodate bridge dies or conductive posts. This segmentation allows independent optimization of each component while maintaining overall interconnection reliability, resolving the contradiction between reliability and complexity.
Solution Approach 2:
Bridge dies are disposed within the through-holes of the frame, creating a nested structure where the bridge die is embedded in the frame. This nesting approach improves interconnection reliability by providing stable mechanical and electrical coupling while maintaining a compact overall structure.
2Stability of the object's composition
If conventional interposer structures are used, then device complexity is lower, but warpage characteristics worsen
Solution Approach 1:
The interposer employs a composite structure combining frame material, encapsulant material, and bridge die materials with different thermal expansion coefficients. This composite construction balances internal stresses and improves warpage characteristics by compensating for thermal and mechanical deformations.
Solution Approach 2:
The frame structure provides localized structural support at critical positions, while the encapsulant provides uniform support across the entire interposer surface. This local quality differentiation optimizes warpage characteristics by addressing specific stress concentration areas without increasing overall complexity.
3Reliability
If existing interposer structures are used, then manufacturing process is simpler, but electrical connectivity stability deteriorates
Solution Approach 1:
Conductive posts are pre-formed in the frame before bridge die attachment, and the encapsulant is pre-cured to establish stable electrical pathways. This preliminary action ensures electrical connectivity stability is established early in the manufacturing process, simplifying subsequent assembly steps.
Solution Approach 2:
The encapsulant serves as an intermediary material that provides both mechanical support and electrical insulation while allowing conductive posts to pass through. This intermediary structure stabilizes electrical connectivity by protecting conductive pathways while maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor package includes a frame having a first surface and a second surface, and including a wiring structure and a through-hole. The package further includes a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer on the first insulating layer and connected to the wiring structure, a bridge die in the through-hole and having an interconnector, and an encapsulant surrounding the bridge die, and covering the second surface of the frame. The package further includes a second redistribution structure disposed on the encapsulant, and including a second insulating layer and a second redistribution layer on the second insulating layer and connected to the interconnector and the wiring structure, and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector.