Semiconductor Package Interposer Without Through Silicon Vias
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Solution Overview
Problem
There is a need for semiconductor packages that are thin, light, and have increased storage capacity while being electrically connected efficiently, with reduced manufacturing costs and improved structural reliability.
Innovation Solution
The semiconductor package design includes a package substrate with an interposer that does not have through silicon via connections, using adhesive and molding layers for structural stability, and a method of manufacturing that connects semiconductor chips through an interposer without aligning them separately, allowing for efficient electrical connections and reduced manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon via connections are used in the interposer to directly connect semiconductor chips to the package substrate, then electrical connection efficiency is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the through silicon via structure from the interposer, extracting the complex manufacturing process while maintaining electrical connectivity through alternative means (wire bonds or trace connections on the interposer surface), thereby simplifying manufacturing without sacrificing electrical connection functionality
Solution Approach 2:
The interposer serves as an intermediary component between the semiconductor chips and package substrate, providing electrical connection through its surface traces or wire bond interfaces rather than requiring through-silicon vias, thus mediating the connection in a simpler manner
2Quantity of substance
If multiple semiconductor chips are integrated in a compact arrangement to increase storage capacity, then storage capacity is improved, but structural reliability and ease of manufacturing decrease
Solution Approach 1:
The patent divides the semiconductor system into separate functional components (multiple semiconductor chips) that are individually mounted on the package substrate with an interposer, allowing each chip to be manufactured and tested separately while achieving high storage capacity through integration of multiple units
Solution Approach 2:
The patent arranges multiple semiconductor chips in a two-dimensional layout on the package substrate rather than stacking them vertically, using the lateral space efficiently to increase storage capacity while maintaining structural reliability through planar configuration
3Length of moving object
If semiconductor chips are arranged in a compact thin profile to reduce package thickness, then package thickness is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary mounting and connection of semiconductor chips to the package substrate before final encapsulation, allowing for adjustment and verification of connections while the structure is still accessible, thereby reducing the need for extremely high precision in the final thin profile configuration
Solution Approach 2:
The interposer acts as a mediator between the semiconductor chips and package substrate, providing a stable intermediate platform that facilitates connection even in thin profiles, reducing the direct alignment precision requirements between chips and substrate
Data Source
AI summary
A semiconductor package includes a package substrate, an interposer on the package substrate, a lower molding layer on the package substrate and surrounding the interposer, a first semiconductor chip on the lower molding layer, a chip connection terminal between the first semiconductor chip and the package substrate and surrounded by the lower molding layer, a second semiconductor chip on the lower molding layer and at an outer side of the first semiconductor chip, interposer connection terminals that connect the first and second semiconductor chips to the interposer, and an upper molding layer on the lower molding layer and surrounding the first and second semiconductor chips.