Semiconductor Package Non-Silicon Interposer Pitch Segmentation
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Solution Overview
Problem
Existing three-dimensional semiconductor packages using TSV interposers for electrical interconnections between dies are costly due to the need for fine-pitch interconnections in a small portion of the interposer, while most regions are designed for relatively great pitch, leading to increased thickness and manufacturing costs.
Innovation Solution
A semiconductor package device featuring a first interconnection structure with a specific pitch, surrounded by a non-silicon interposer with a larger second pitch, allowing for fine-pitch interconnections only where needed, eliminating the need for a TSV interposer by embedding fine-pitch interconnections within a coarse-pitch structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a TSV interposer is used to provide electrical interconnection between two dies, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The interconnection structure is segmented into two distinct pitch regions: a first pitch region for fine-pitch interconnections between dies and a second pitch region for coarse-pitch interconnections to external components. This segmentation allows each region to be optimized independently, reducing overall manufacturing cost while maintaining necessary electrical connectivity.
Solution Approach 2:
Different pitch specifications are applied to different spatial locations within the interposer: fine pitch in the region where dies are mounted and coarse pitch in the region for external interconnections. This local quality approach ensures that expensive fine-pitch processing is only applied where absolutely necessary, reducing manufacturing cost while preserving electrical connectivity where required.
2Reliability
If fine-pitch interconnection is provided in a small portion of the interposer, then electrical interconnection between dies is achieved, but the interposer thickness increases
Solution Approach 1:
The patent transitions from vertical through-silicon vias (TSV) that require significant thickness to a planar redistribution layer approach where interconnections are formed in horizontal planes. The first and second pitch regions are implemented as layered conductive structures that achieve fine-pitch interconnection without requiring the interposer to be thick, thus reducing the length dimension while maintaining electrical interconnection capability.
3Ease of manufacture
If most regions of the interposer are designed for relatively great pitch, then manufacturing cost is reduced, but electrical interconnection capability is compromised
Solution Approach 1:
The interposer is divided into functionally distinct regions: a first pitch region with fine-pitch interconnections for die-to-die connectivity and a second pitch region with coarse-pitch interconnections for external connectivity. This segmentation ensures that electrical interconnection capability is maintained in the first region while the second region benefits from reduced manufacturing cost associated with coarse-pitch processing.
Solution Approach 2:
Fine-pitch interconnection quality is localized to the first pitch region where die mounting occurs, while the second pitch region uses coarse-pitch design for cost-effective external interconnections. This local quality differentiation ensures that high electrical interconnection capability is provided only where necessary, balancing reliability requirements with manufacturing cost reduction.
Data Source
AI summary
A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.