Semiconductor Package Interposer for Warping-Free Chip Bonding
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Solution Overview
Problem
The challenge of integrating semiconductor chips into a substrate has been limited by the inability to effectively bond them due to mismatched thermal expansion coefficients, leading to warping and incomplete physical and electrical coupling, which affects the reliability and performance of integrated circuit packages.
Innovation Solution
The integration of semiconductor chips is enhanced by using an interposer with a redistribution structure that includes a molding compound and a redistribution layer, which reduces thermal expansion mismatch and improves electrical connectivity, thereby minimizing warping and electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor chips are directly bonded to a substrate, then the integration density is improved, but warping occurs due to thermal expansion mismatch
Solution Approach 1:
An interposer structure is introduced as an intermediary component between the semiconductor chip and substrate. The interposer includes a first redistribution structure with a first co-efficient of thermal expansion matched to the chip, and a second redistribution structure with a second co-efficient of thermal expansion matched to the substrate. This gradient structure acts as a thermal expansion bridge, eliminating warping while enabling direct bonding and high integration density.
2Area of stationary object
If semiconductor chips are directly bonded to a substrate, then the area is reduced, but incomplete physical and electrical coupling occurs
Solution Approach 1:
The interposer with redistribution structures serves as a mediator that redistributes bonding forces and electrical connections. The first redistribution structure redistributes forces from the chip bonding area, while the second redistribution structure redistributes forces to the substrate bonding area. This prevents stress concentration and ensures complete, reliable physical and electrical coupling even with reduced overall bonding area.
3Ease of manufacture
If thermal expansion mismatch is not addressed, then the manufacturing process is simplified, but electrical shorting between conductive connectors occurs
Solution Approach 1:
The interposer with thermally-matched redistribution structures acts as a mediator that prevents warping during manufacturing and operation. By eliminating warping through proper thermal expansion matching, the conductive connectors maintain proper spacing and alignment, preventing electrical shorting while keeping the manufacturing process relatively simple.
Solution Approach 2:
The co-efficient of thermal expansion parameter is carefully controlled and matched across different layers of the interposer structure. The first redistribution structure is designed with a co-efficient matched to the chip, and the second redistribution structure is designed with a co-efficient matched to the substrate, creating a gradient that prevents warping and electrical shorting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved reliability and performance of integrated circuit packages by reducing warping and enhancing electrical coupling, ensuring stable and efficient operation.
Implementation Method 1
mismatched thermal expansion coefficients, leading to warping
Implementation Method 2
improves electrical connectivity, thereby minimizing warping and electrical shorting
Data Source
AI summary
A method includes forming a first redistribution structure over a carrier, where forming the first redistribution structure includes forming a plurality of first organic polymer layers over the carrier, and forming a plurality of first conductive lines in the plurality of first organic polymer layers, attaching a first package structure to the first redistribution structure, the first package structure including a first semiconductor die, a molding material that surrounds an entirety of a perimeter of the first semiconductor die, and a second redistribution structure on bottom surfaces of the first semiconductor die and the molding material, dispensing a first underfill into a first gap between the plurality of first conductive lines and the first package structure, bonding a substrate to the first redistribution structure using first conductive connectors, and dispensing a second underfill into a second gap between the substrate and the first redistribution structure.