Semiconductor Package I/O Density via Plated Leadframe

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Solution Overview

Problem

Conventional semiconductor packages face challenges in increasing I/O density due to space occupation by tie bars and the mechanical weaknesses caused by the sawing process, which limits the number of leads and pads, and introduces susceptibility to solder shorting and mechanical stress.

Innovation Solution

The semiconductor package employs multiple plating and chemical etching processes to form die pads, conductive rings, and I/O pads without the need for sawing, allowing for increased I/O density and improved mechanical interlock through inclined surfaces and protruding plated layers, eliminating the need for tie bars and reducing manufacturing-induced defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If tie bars are used to support the die pad and ground ring within the outer frame, then structural support is provided, but space is occupied that could be used for additional leads or I/O pads

Engineering Contradiction:
Improvenumber of leads or I/O padsVSAvoidstructural support requirements
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent removes tie bars from the leadframe structure entirely. Instead of using separate tie bar elements to support the die pad and ground ring, the invention integrates support functions directly into the outer frame through chemically etched recesses and protruding plated layers, eliminating the need for additional space-consuming tie bar components.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines multiple functions into the outer frame structure. The outer frame simultaneously provides structural support, electrical connection, and mechanical attachment for the die pad and ground ring, eliminating the need for separate tie bar elements and thereby increasing available space for I/O pads.

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If the pitch of leads at the periphery is narrowed to increase the number of leads, then I/O density increases, but susceptibility to solder shorting increases

Engineering Contradiction:
Improvenumber of leadsVSAvoidsusceptibility to solder shorting
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a two-dimensional peripheral lead arrangement to a three-dimensional configuration by providing inclined surfaces on the die pad and ground ring that extend upwardly. This vertical dimension allows leads to be attached at angles, effectively increasing the usable perimeter for lead placement without reducing pitch, thereby maintaining solder reliability while increasing I/O density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If a sawing process is used to facilitate the formation of multiple columns and rows of leads, then lead arrangement flexibility increases, but mechanical weaknesses and manufacturing defects increase

Engineering Contradiction:
Improvelead arrangement flexibilityVSAvoidmechanical weaknesses and defects
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent replaces the mechanical sawing process with chemical etching to form recesses in the outer frame. This chemical process eliminates mechanical stresses, chip-outs, and cracks associated with sawing, while still providing the necessary lead arrangement flexibility through precisely controlled etched features.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces chemically etched recesses as intermediary features that facilitate lead attachment and arrangement. These recesses serve as mediators between the outer frame and the leads, providing mechanical support and electrical connection without requiring destructive sawing operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Quantity of substance

If multiple plating and chemical etching processes are used to form die pads and leads, then I/O density increases and mechanical strength improves, but manufacturing complexity increases

Engineering Contradiction:
ImproveI/O densityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent makes the outer frame multi-functional by having it simultaneously provide structural support, electrical connection, mechanical attachment, and lead positioning. The chemically etched recesses and protruding plated layers perform multiple functions, reducing the need for separate components and processes despite the advanced manufacturing techniques used.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances I/O density, strengthens the mechanical structure, and reduces the risk of solder shorting and mechanical stress, enabling higher performance and functionality in smaller, lighter semiconductor packages.

Implementation Method 1

multiple plating and chemical etching processes to form die pads, conductive rings, and I/O pads

Methodology Applied
Scientific EffectElectroplating: Electroplating

Implementation Method 2

multiple plating and chemical etching processes to form die pads, conductive rings, and I/O pads

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS8227921B1Semiconductor package with increased I/O density and method of making same
Publication Date: 2012.07.24 AMKOR TECH SINGAPORE HLDG PTE LTD
  • US8227921B1 patent drawing
  • US8227921B1 patent drawing
  • US8227921B1 patent drawing

AI summary

The present invention is related to a semiconductor package and method for fabricating the same wherein the semiconductor package includes a die pad having a semiconductor die mounted thereto, and two or more sets of leads or I/O pads which extend at least partially about the die pad in spaced relation thereto and to each other. The formation of the die pad and the leads of the leadframe are facilitated by the completion of multiple plating and chemical etching processes in a prescribed sequence. The present invention is further related to a semiconductor package and method for fabricating the same wherein the semiconductor package includes a semiconductor die electrically connected a plurality of leads or I/O pads via a flip chip type connection, each of the leads being formed by the completion of multiple plating and chemical etching processes in a prescribed sequence.