Stacked Semiconductor Package Structure for Isolated Through-Electrodes
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing size, weight, and manufacturing costs while maintaining electrical characteristics, particularly in the wafer-level package design where the absence of a molding process complicates the integration of semiconductor chips and redistribution patterns.
Innovation Solution
The proposed semiconductor device incorporates a stack of packages with redistribution substrates, semiconductor chips, and through-electrodes, where each package has a unique redistribution pattern and through-electrode configuration, allowing for electrical insulation and alignment to enhance bandwidth and simplify manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a wafer-level package is used without a molding process, then manufacturing complexity is reduced and package thickness is decreased, but electrical insulation and integration become more difficult
Solution Approach 1:
The patent divides the package structure into multiple segments including a first package and a second package stacked vertically. Each package contains separate through-electrodes (first through-electrode and second through-electrode) that are spatially segmented and electrically isolated from each other within the same molding layer, enabling independent electrical pathways while maintaining insulation.
Solution Approach 2:
The patent transitions from planar electrical connections to three-dimensional vertical stacking. The first and second through-electrodes are positioned at different vertical levels and lateral positions within the molding layer, utilizing the third dimension (height) to achieve both electrical connection and insulation simultaneously. The first through-electrode connects to the first redistribution pattern while the second through-electrode connects to the second redistribution pattern, with electrical insulation maintained through spatial separation in the vertical dimension.
2Area of stationary object
If packages are stacked to reduce size, then package footprint is decreased, but alignment precision and electrical connection reliability become more challenging
Solution Approach 1:
The molding layer serves multiple functions simultaneously: it provides electrical insulation between the first and second through-electrodes, mechanically supports both packages in the stacked configuration, and enables vertical alignment of the through-electrodes with the redistribution patterns. This multi-functional design simplifies the overall structure while maintaining manufacturing precision.
Solution Approach 2:
The first redistribution pattern and second redistribution pattern act as intermediary elements between the through-electrodes and the semiconductor chips. The first through-electrode connects to the first redistribution pattern, which in turn connects to the first semiconductor chip, while the second through-electrode connects to the second redistribution pattern and second semiconductor chip. This intermediary structure facilitates precise alignment and electrical connection in the stacked configuration.
Data Source
AI summary
A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.