Encapsulated Semiconductor Package Laser-Ablated Redistribution

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Solution Overview

Problem

Existing semiconductor packaging techniques face challenges in reducing interconnect density and increasing design flexibility, particularly in stacking grid arrays and incorporating metal shield caps without additional through vias.

Innovation Solution

A method involving laser-ablation of via holes through encapsulation, followed by deposition of conductive material to form blind vias, and the formation of buildup dielectric layers with laser-ablated artifacts filled with metal to create electrically conductive patterns, allowing for redistribution and integration of metal layers atop semiconductor packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional through vias are used to connect metal shield caps to ground terminals, then electrical connection is achieved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:

Improveelectrical connectionVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the through via structure from the design and replaces it with blind vias that terminate at the metal shield cap without penetrating through the substrate. This eliminates the need for through vias while maintaining electrical connection functionality, thereby reducing device complexity and manufacturing difficulty

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the via structure into two types: blind vias that terminate at the metal shield cap and through vias that extend through the substrate. This segmentation allows the metal shield cap to be electrically connected without requiring traditional through vias, simplifying the overall structure

Inventive Principle:

Principle #1Segmentation

2Productivity

If interconnect density is increased to accommodate stacking requirements, then component integration is improved, but design flexibility decreases

Engineering Contradiction:

Improvepackaging efficiencyVSAvoiddesign flexibility

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent introduces buildup dielectric layers with metallization patterns that create additional horizontal interconnection dimensions. This allows signals to be redistributed and routed in multiple layers, enabling component stacking and improved packaging efficiency while maintaining design flexibility through multi-layer routing options

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If metal layers are integrated atop semiconductor packages, then functionality is enhanced, but manufacturing complexity increases

Engineering Contradiction:

ImprovefunctionalityVSAvoidmanufacturing complexity

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent incorporates metallization patterns within the buildup dielectric layers during the packaging manufacturing process, before final assembly. This preliminary integration of metal layers simplifies subsequent manufacturing steps and reduces overall manufacturing complexity while enhancing package functionality

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent merges the formation of buildup dielectric layers with the integration of metallization patterns into a single manufacturing process flow. This combining of steps reduces manufacturing complexity while achieving the desired functionality of integrated metal layers atop the semiconductor package

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces interconnect density, enhances design flexibility, and enables the integration of metal shield caps without additional through vias, facilitating the stacking of components and improving the overall packaging efficiency.

Implementation Method 1

Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

Laser-ablated artifacts are laser-ablated in the first buildup dielectric layer

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Implementation Method 3

conductive material is deposited within the via holes to form vias

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS10811277B2Encapsulated semiconductor package

Publication Date: 2020.10.20 AMKOR TECH SINGAPORE HLDG PTE LTD

AI summary

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.