Semiconductor Package Marking to Reduce Laser-Induced Defects
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging techniques for stacked semiconductor devices, where current bonding processes are complex and require improvements for smaller, faster, and more efficient integration of electronic components.
Innovation Solution
A method involving a carrier substrate with an adhesive layer, polymer layer, and seed layer, where through vias are formed and semiconductor devices are bonded and encapsulated, with a redistribution layer for interconnection, and a marking process using laser pulses to create identifying marks without damaging the devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bonding processes are used to stack semiconductor devices, then integration density is improved, but process complexity increases
Solution Approach 1:
The patent segments the bonding process into multiple controlled stages: first forming adhesive layers on separate substrates, then bonding substrates together, followed by sequential formation of through vias, polymer layers, and seed layers. This segmentation allows each step to be optimized independently, reducing overall process complexity while achieving high integration density through stacked device architecture.
Solution Approach 2:
The patent applies preliminary action by pre-forming adhesive layers on substrates before bonding, and by preparing through vias and conductive layers in advance on separate substrates. This preliminary preparation enables more controlled and simpler bonding operations, as components are ready-to-assemble rather than requiring complex in-situ fabrication during the bonding process.
2Quantity of substance
If feature size is reduced for miniaturization, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs nested doll by creating multi-layered structures where smaller features are embedded within larger structures. Through vias penetrate through multiple layers (encapsulant, polymer layer, seed layer), and conductive features are nested within dielectric layers. This nested architecture allows miniaturization while maintaining manufacturing precision through hierarchical fabrication control.
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration by forming through vias that connect multiple substrate layers vertically. This dimensional change allows continued integration density improvement without further reducing lateral feature sizes, thereby easing manufacturing precision requirements while achieving miniaturization goals.
3Measurement precision
If laser marking is used for identification, then marking precision is improved, but risk of device damage increases
Solution Approach 1:
The patent applies beforehand cushioning by forming a polymer layer between the seed layer and the marking surface. This polymer layer acts as a cushioning buffer that absorbs and dissipates laser energy, preventing direct laser damage to underlying semiconductor devices while still allowing precise laser marking on the polymer layer surface for device identification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient packaging of semiconductor devices with enhanced miniaturization, reduced defects, and improved thermal control, allowing for higher integration density and yield in semiconductor devices.
Implementation Method 1
a marking process using laser pulses to create identifying marks without damaging the devices
Data Source
AI summary
A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.