Encapsulated Semiconductor Package Laser-Ablated Vias
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Solution Overview
Problem
Existing semiconductor packaging techniques face challenges in increasing packaging density and flexibility while reducing interconnect densities, and in providing a metal shield cap without requiring additional through vias.
Innovation Solution
A method of manufacturing a semiconductor package involves mounting and electrically connecting a semiconductor die to a substrate, encapsulating it, laser-ablating via holes, and depositing conductive material to form blind vias, and creating a buildup dielectric layer with laser-ablated artifacts filled with a metal layer to form conductive patterns, allowing for redistribution and integration of components without additional vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional through vias are used to connect metal shield cap to ground terminal, then electrical connection is achieved, but device complexity and manufacturing difficulty increase due to additional vias required
Solution Approach 1:
The patent extracts the electrical connection function from the traditional through-via structure and relocates it to the bottom surface of the encapsulation. The metal shield cap is connected to ground through conductive structures formed on the bottom surface, eliminating the need for additional through vias penetrating the entire encapsulation thickness.
Solution Approach 2:
The patent transitions from a vertical through-via connection approach to a horizontal bottom-surface connection approach. Instead of creating vias that extend through the depth of the encapsulation, the electrical connection is established on the bottom surface plane, reducing structural complexity.
2Quantity of substance
If interconnect density is increased to accommodate more components, then packaging density improves, but manufacturing complexity and design flexibility worsen
Solution Approach 1:
The patent segments the interconnect structure into multiple functional layers: bottom surface conductive structures, encapsulation with integrated vias, and top surface metal patterns. This segmentation allows independent optimization of each layer, enabling high packaging density without proportionally increasing overall interconnect complexity.
Solution Approach 2:
The encapsulation structure serves multiple functions: it provides mechanical support, contains the semiconductor device, and integrates electrical interconnects through its thickness. This multi-functionality reduces the need for separate dedicated interconnect structures, thereby increasing packaging density without linearly increasing complexity.
3Reliability
If metal shield cap is added for electromagnetic shielding, then reliability improves, but device complexity increases due to additional through vias required
Solution Approach 1:
The patent merges the electromagnetic shielding function with the existing ground connection infrastructure. The metal shield cap is electrically connected to ground terminals through conductive structures that are integrated into the encapsulation's bottom surface and internal vias, combining shielding and grounding functions into a unified structure rather than adding separate through vias.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances packaging density and flexibility by reducing interconnect densities and enabling a metal shield cap without additional vias, facilitating the stacking of components and improving design flexibility.
Implementation Method 1
Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias
Implementation Method 2
Laser-ablated artifacts are laser-ablated in the first buildup dielectric layer. The laser-ablated artifacts in the first buildup dielectric layer are filled with a first metal layer to form a first electrically conductive pattern
Data Source
AI summary
An encapsulated semiconductor package. As non-limiting examples, various aspects of the present disclosure provide an integrated circuit package comprising a laminate, an integrated circuit die coupled to the laminate, an encapsulant surrounding at least top and side surface of the integrated circuit die, a conductive column extending from the top side of the integrated circuit die to a top side of the encapsulant, and a signal distribution structure on a top side of the encapsulant.