Method of fabricating semiconductor structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Circuit (SoIC) components due to limitations in current packaging processes, which affect miniaturization, speed, bandwidth, power consumption, and latency.
Innovation Solution
The described process involves fabricating top and bottom tier semiconductor dies with advanced packaging techniques, including wafer-level chip probing, solder material layer removal, protection layer formation, thinning, frame mounting, and wafer sawing, along with the use of conductive pillars and insulating encapsulation to create a robust and reliable package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging processes are used for SoIC components, then manufacturing simplicity is maintained, but integration density and performance (miniaturization, speed, bandwidth, power consumption, latency) deteriorate
Solution Approach 1:
The patent combines multiple packaging operations into integrated process steps. Specifically, the molding compound application and curing process simultaneously achieves encapsulation, stress relief, and electrical insulation in one operation. The wire bonding process integrates metal deposition, wire placement, and bonding in a single automated sequence, improving integration density while managing process complexity through consolidation of functions.
Solution Approach 2:
The packaging process is divided into distinct modular stages: substrate preparation, wire bonding, molding compound application, and curing. Each stage can be independently optimized and controlled. The wire bonding process itself is segmented into metal layer deposition, wire placement, and bonding sub-steps, allowing precise control over each function while maintaining overall process manageability.
2Manufacturing precision
If advanced packaging techniques are implemented to improve integration density, then performance is enhanced, but device complexity and process steps increase
Solution Approach 1:
The patent merges multiple functions into the molding compound application and curing process. This single integrated operation provides encapsulation for protection, stress relief for reliability, and electrical insulation for functionality. By combining these functions into one process step rather than separate operations, the patent achieves high integration density while limiting the increase in overall process complexity.
Solution Approach 2:
The molding compound serves multiple purposes simultaneously: it provides mechanical protection and encapsulation, stress relief to prevent cracking, electrical insulation to prevent short circuits, and structural support for the bonded wires. This multi-functionality reduces the need for additional separate process steps, allowing advanced packaging techniques to improve integration density without proportionally increasing device complexity.
Data Source
AI summary
A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.