Semiconductor Package Dielectric Liner Electrical Isolation
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Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in isolating power devices from integrated circuit chips, leading to increased packaging costs, size, and performance issues due to defects in insulating adhesive films and parasitic mechanisms caused by close die packaging.
Innovation Solution
A semiconductor package design featuring a dielectric liner layer between the die and the substrate, which completely covers the bottom surface and can also be on the sidewalls, electrically isolating the die from the die paddle and preventing parasitic interference, and using thicker galvanic interconnects for improved current carrying capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple dies are closely packaged within a single semiconductor package, then the package size is reduced, but parasitic mechanisms begin to operate and deteriorate the performance of the semiconductor device
Solution Approach 1:
A dielectric liner layer is introduced as an intermediary between the first die and the substrate. This liner layer completely covers the bottom surface of the first die and extends along the sidewalls, providing electrical isolation that prevents parasitic mechanisms while allowing the dies to be closely packaged together
2Reliability
If conventional insulating adhesive films are used to isolate power devices from integrated circuit chips, then electrical isolation is achieved, but the packaging cost increases and defects in the adhesive film can occur
Solution Approach 1:
The invention changes the material parameter from conventional insulating adhesive films to a dielectric liner layer deposited through CVD or PECVD processes. This dielectric liner layer provides superior electrical isolation properties and can be precisely controlled in thickness (100 nm to 10 μm), eliminating defects associated with adhesive films while reducing packaging costs
3Reliability
If a dielectric liner layer is deposited under the bottom surface of the first die, then electrical isolation from the die paddle is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The dielectric liner layer is deposited in advance before the first die is mounted onto the substrate. This preliminary deposition action simplifies the overall manufacturing process by eliminating the need for complex post-mounting isolation techniques, while ensuring complete coverage of the bottom surface and sidewalls of the first die
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric liner layer enhances the reliability and performance of semiconductor packages by preventing dielectric breakdown and reducing parasitic interference, while the galvanic interconnects provide higher current carrying capacity, addressing the limitations of conventional packaging methods.
Implementation Method 1
A dielectric liner layer is disposed under the first die and between the first die and the substrate. The dielectric liner layer completely covers a bottom surface of the first die.
Implementation Method 2
A bond layer disposed between the substrate and the dielectric liner layer.
Implementation Method 3
a first die embedded within an encapsulant and disposed over a substrate
Data Source
AI summary
In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. A bond layer is disposed between the substrate and the dielectric liner layer.