Semiconductor Package Structure for Dual-Sided Liquid Cooling
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Solution Overview
Problem
High-end computing applications face thermal management challenges due to escalating processor power and memory bandwidth gaps, leading to overheating and reduced performance in 3D HBM DRAM stacks, which limits the potential of processor performance gains and increases energy consumption in data centers.
Innovation Solution
A semiconductor package design featuring a substrate with fluidic cavities for direct-to-chip liquid cooling, allowing liquid to flow between cavities and directly contact processor and memory dies, enabling dual-sided cooling and enhanced heat dissipation through a cold plate in direct thermal contact with the processor and memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 3D HBM DRAM stacks are placed closer to processor in 2.5D IC configuration to reduce memory latency and increase bandwidth, then memory performance is improved, but thermal management becomes more difficult and heat dissipation is reduced
Solution Approach 1:
The patent transitions from traditional 2D memory packaging to 3D stacked HBM DRAM architecture, vertically stacking multiple DRAM dies (4, 8, or 12 layers) on a control logic die. This three-dimensional configuration dramatically increases memory bandwidth and reduces latency by placing memory closer to the processor in the vertical dimension, while managing the increased thermal density through advanced cooling integration.
Solution Approach 2:
The patent introduces a cold plate as an intermediary thermal management component that directly contacts the processor and memory stack. The cold plate serves as a heat sink and liquid cooling interface, mediating heat transfer from the high-power processor (700W for GPUs, 400W for CPUs) and memory stack to a coolant flow, enabling effective thermal management of the densely packed 2.5D IC configuration.
2Power
If processor power is increased to exceed 1000 W/chip to handle escalating data traffic, then computing performance is improved, but heat generation increases and cooling requirements become more stringent
Solution Approach 1:
The patent employs liquid cooling through a cold plate system where coolant flows through channels in direct contact with the processor and memory stack. This hydraulic cooling system efficiently removes heat from high-power processors (currently 700W for GPUs, 400W for CPUs, with projections exceeding 1000W/chip) by transferring thermal energy to the circulating coolant, enabling sustained high-performance operation.
Solution Approach 2:
The patent changes the thermal management approach from air cooling to liquid cooling, fundamentally altering the heat dissipation parameters. The cold plate system enables direct liquid-to-chip cooling with superior thermal conductivity, allowing the processor and memory stack to operate at higher power densities while maintaining safe operating temperatures through enhanced heat transfer coefficients.
3Quantity of substance
If multiple DRAM dies are vertically stacked to increase memory density and bandwidth, then memory capacity is improved, but heat dissipation paths are limited and bottom tiers overheat
Solution Approach 1:
The patent segments the memory system into multiple discrete DRAM dies stacked vertically (4, 8, or 12 layers) on a control logic die. Each DRAM die layer contributes to increased memory density and bandwidth while the segmentation allows for distributed thermal management. The cold plate cooling system provides uniform heat removal across the entire stack, preventing localized overheating in bottom tiers despite the increased density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates thermal management issues by improving cooling performance, allowing for higher power processors and memory operations, reducing energy consumption, and enhancing the integration of high-power components in 2.5D and 3D ICs, thereby addressing the 'memory wall' effect and thermal challenges in data centers.
Implementation Method 1
a cold plate over the first die with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first cavity and the second cavity
Implementation Method 2
allowing liquid to pass through... allowing the liquid to flow between the first cavity and the second cavity
Data Source
AI summary
A semiconductor package includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and/or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling. The semiconductor package further includes an underground interconnection (UGI) disposed in a STI region of the processor die.