Semiconductor Package With Embedded Local Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and communication bandwidth between integrated circuit dies due to warpage mismatch and coefficient of thermal expansion (CTE) mismatch between package structures, which limits the need for interposers and increases fabrication complexity.
Innovation Solution
The implementation of a system-on-integrated-substrate (SoIS) package with embedded local interconnect components in a redistribution structure, which provides electrical connection between integrated circuit dies and a core substrate, reducing the need for interposers by increasing communication bandwidth and maintaining low contact resistance and high reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional package structures are used with interposers, then reliability is maintained, but device complexity and fabrication complexity increase
Solution Approach 1:
The patent removes the interposer component from the package structure entirely. The redistribution structure is directly integrated into the core substrate, eliminating the need for a separate interposer layer. This extraction simplifies the overall device architecture while maintaining electrical connection functionality between stacked semiconductor packages.
Solution Approach 2:
The patent combines the redistribution structure and core substrate into a single integrated component. The redistribution structure is formed directly on the core substrate, merging two previously separate elements into one unified structure, thereby reducing packaging complexity and the number of assembly steps.
2Reliability
If interposers are used to connect integrated circuit dies, then electrical connection is achieved, but manufacturing precision requirements increase due to warpage mismatch
Solution Approach 1:
The interposer is removed from the structure, eliminating the warpage mismatch problem that occurs between interposers and core substrates. By directly integrating the redistribution structure onto the core substrate, the patent eliminates the additional interface that would require precise warpage control.
3Quantity of substance
If package-on-package technology is implemented, then integration density increases, but thermal expansion mismatch between packages worsens
Solution Approach 1:
The redistribution structure and core substrate are merged into a single integrated component with unified material composition. This integration ensures consistent thermal expansion characteristics throughout the structure, eliminating the thermal expansion mismatch that would occur between separate package layers with different materials.
4Adaptability or versatility
If multiple separate components are assembled, then functionality is achieved, but contact resistance increases
Solution Approach 1:
The redistribution structure is formed as an integrated part of the core substrate through direct deposition and patterning processes. This merging eliminates intermediate bonding interfaces that would introduce contact resistance, creating direct electrical pathways between the stacked semiconductor packages and the core substrate.
Data Source
AI summary
In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.