Semiconductor Package Redistribution Circuit for Low-Stress Plating
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently forming redistribution layers with high mechanical strength and reduced stress, while maintaining alignment and alignment flexibility, often requiring additives that introduce impurities and increase production costs.
Innovation Solution
The formation of redistribution circuit layers using a plating process at a current density of 4-6 amperes per square decimeter (ASD) without additives, resulting in structures with coplanar surfaces and improved mechanical strength, reduced stress, and enhanced alignment capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electrolytic plating with additives (suppressors, promoters, brighteners) is used to form redistribution layers, then coating performance is improved (gloss, physical properties, throwing power, blind via hole filling), but impurities are introduced and production costs increase
Solution Approach 1:
The patent removes additives (suppressors, promoters, brighteners) from the electrolytic plating solution, extracting only the essential copper sulfate and water components. This extraction eliminates impurity introduction while maintaining core plating functionality through optimized current density parameters.
Solution Approach 2:
The patent changes the operational parameters by specifying a current density range of 2-10 ASD (amperes per square decimeter) for forming redistribution layers. This parameter optimization compensates for the absence of additives, achieving proper coating performance through controlled electrical conditions rather than chemical additives.
2Manufacturing precision
If electrolytic plating with additives is used to form redistribution layers, then coating performance is improved (gloss, physical properties, throwing power, blind via hole filling), but production costs increase
Solution Approach 1:
The patent extracts and eliminates expensive additive chemicals (suppressors, promoters, brighteners) from the plating solution, retaining only copper sulfate and water. This reduction in chemical complexity directly lowers material costs while maintaining coating quality through parameter control.
Solution Approach 2:
The patent employs a simplified plating solution with shorter processing times achieved through optimized current density. This approach uses cheaper, more readily available chemicals and reduces overall process complexity, making the manufacturing more cost-effective.
3Reliability
If conventional plating processes are used, then redistribution layers can be formed, but mechanical strength and stress resistance are insufficient
Solution Approach 1:
The patent optimizes the current density parameter to 2-10 ASD, which controls the deposition rate and crystal structure of the copper layer. This parameter range produces denser, more mechanically robust redistribution layers with improved strength and reduced internal stress compared to conventional plating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances production efficiency, reduces production costs, and improves structural integrity and alignment flexibility, minimizing voids and delamination risks, while allowing for reduced pitch between conductive bumps and eliminating unnecessary keep-out zones.
Implementation Method 1
Electrolytic plating is used for forming redistribution layers on semiconductor devices, for example. In copper sulfate electrolytic plating for example
Data Source
AI summary
A semiconductor package includes a semiconductor die including an active surface and an electrical terminal on the active surface, and a redistribution circuitry disposed on the active surface of the semiconductor die and connected to the electrical terminal. A top surface of the redistribution circuitry includes a planar portion and a concave portion connected to the planar portion, the concave portion is directly over the electrical terminal, and a minimum distance measured from a lowest point of the concave portion to a virtual plane where the planar portion is located is equal to or smaller than 0.5 μm.