Semiconductor Package Low Thermal Expansion Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The difference in thermal expansion between semiconductor chips and plastic packages leads to stress concentration and reliability issues, such as chip cracking and wiring breakage, which existing solutions like coreless packages or ceramic substrates cannot adequately address due to limitations in versatility and material compatibility.
Innovation Solution
A semiconductor package with a low thermal expansion material layer bonded to the rear surface of the build-up wiring layer, matching the thermal expansion coefficient of the semiconductor chip, is manufactured using a method involving low thermal expansion material plates, resin curing, and build-up wiring layer formation to reduce thermal expansion differences and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a plastic laminate package is used, then the package structure is simple and easy to manufacture, but the difference in thermal expansion between the package and semiconductor chip causes stress concentration and reliability issues
Solution Approach 1:
The patent uses a composite material structure consisting of a plastic laminate package combined with a CTE control layer made of low thermal expansion material (such as glass or ceramic). This composite structure allows the package to maintain the manufacturing simplicity of plastic laminate while the CTE control layer reduces thermal expansion difference with the semiconductor chip, thereby decreasing stress concentration and improving connection reliability at the C4 bonding interface.
2Stress or pressure
If a coreless package structure is used, then stress in the intrachip dielectric layer is reduced, but new problems of stress concentration at connection parts and package warpage occur
Solution Approach 1:
The patent applies local quality by selectively placing a CTE control layer only at specific regions where thermal expansion mismatch causes problems (such as near the C4 connection parts), rather than uniformly modifying the entire package structure. This localized approach reduces stress at critical connection points while maintaining the overall coreless package structure's benefits of reduced intrachip dielectric stress.
3Reliability
If a ceramic substrate is used, then thermal expansion is reduced and matched to semiconductor chip, but the structure lacks versatility and cannot be applied to other substrates
Solution Approach 1:
The patent creates a universal solution by designing a CTE control layer that can be integrated with various substrate types (plastic laminate, ceramic, glass, or other materials). The CTE control layer acts as an adaptable intermediate layer that can be combined with different base materials, allowing the thermal expansion matching benefit to be achieved across multiple package types and substrate materials, thereby providing versatility and broad applicability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces thermal expansion differences between the semiconductor chip and the package, improving connection reliability and preventing warpage, while being applicable to various substrates without the need for specific materials, thus enhancing the overall reliability and manufacturing ease of semiconductor devices.
Implementation Method 1
The difference in coefficient of thermal expansion (CTE) between Si of a semiconductor chip and a plastic package unfavorably results in the reduction of the connection reliability due to the stress concentration at the C4 connection part
Implementation Method 2
pouring a resin in the clearances, and curing the resin to form an integral underlying plate
Data Source
AI summary
A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.