Semiconductor Package Dielectric Layer Stack for Low TTV Thinning
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving uniform thickness across semiconductor dies due to large total thickness variation (TTV) in dielectric layers, which can lead to device failure and reduced production yield.
Innovation Solution
A method involving the formation of a first dielectric layer with a high shrinkage ratio over a wafer, followed by a second dielectric layer with a low shrinkage ratio, resulting in a substantially flat upper surface that allows for even thinning of the wafer and reduction of TTV.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single dielectric layer with high shrinkage ratio is formed and cured, then the dielectric layer achieves adequate mechanical properties and coverage, but the upper surface becomes non-flat with large thickness variation
Solution Approach 1:
The patent divides the single dielectric layer into multiple layers: a first dielectric layer with high shrinkage ratio (50-80%) providing mechanical properties, and a second dielectric layer with low shrinkage ratio (<1%) providing surface flatness. This segmentation allows each layer to fulfill its specific function without compromising the other.
Solution Approach 2:
The patent applies different materials with different shrinkage characteristics to different regions of the dielectric structure. The first dielectric layer material is selected for high shrinkage to achieve adequate mechanical properties, while the second dielectric layer material is selected for low shrinkage to achieve surface flatness, creating local quality optimization.
2Manufacturing precision
If the wafer is thinned to reduce TTV, then uniform die thickness is achieved, but die connectors may be exposed incorrectly or device failure occurs due to excessive thinning
Solution Approach 1:
The patent applies a second dielectric layer with low shrinkage ratio over the first dielectric layer before thinning the wafer. This second layer acts as a cushioning layer that compensates for the high shrinkage of the first layer, maintaining surface flatness and providing a buffer during the thinning process to prevent over-thinning and incorrect exposure of die connectors.
3Manufacturing precision
If multiple dielectric layers with different shrinkage ratios are formed, then surface flatness and TTV are reduced, but the device complexity and manufacturing process steps increase
Solution Approach 1:
The patent changes the shrinkage ratio parameter of the dielectric layers by selecting materials with different shrinkage characteristics. The first dielectric layer uses material with 50-80% shrinkage ratio while the second uses material with <1% shrinkage ratio, allowing TTV reduction through parameter optimization rather than adding excessive structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces TTV across semiconductor dies, preventing device failure and improving production yield by ensuring uniform die thickness and correct electrical connection of die connectors.
Implementation Method 1
the first dielectric layer has a first shrinkage ratio that is larger than a second shrinkage ratio of the second dielectric layer
Implementation Method 2
the second dielectric layer has a second shrinkage ratio that is smaller than the first shrinkage ratio of the first dielectric layer
Data Source
AI summary
A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.