Semiconductor Package Structure for Low-Warpage Multi-Chip Mounting
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Solution Overview
Problem
Semiconductor packages with interposers face challenges in minimizing warpage due to thermal expansion mismatches between materials, which can lead to damage and reliability issues during the mounting of multiple semiconductor devices.
Innovation Solution
A semiconductor package design incorporating a first redistribution structure with a glass base layer and an epoxy mold compound, where the thermal expansion coefficient of the glass is lower than that of the epoxy, ensuring a coplanar surface and reducing warpage by using a bridge chip and conductive pillars for electrical connectivity, and a second redistribution structure with conductive via patterns extending through the layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large area of interposer is used to mount multiple semiconductor devices, then the mounting capacity is improved, but warpage damage increases due to thermal expansion mismatch
Solution Approach 1:
The patent changes the material parameter (thermal expansion coefficient) by selecting glass as the base layer material with a thermal expansion coefficient of 70-90 ppm/°C, which is lower than the epoxy molding compound (15-25 ppm/°C). This parameter selection resolves the warpage issue while maintaining large interposer area for multiple device mounting
Solution Approach 2:
The patent uses a composite structure combining glass base layer with epoxy molding compound, where the glass provides dimensional stability and low thermal expansion, while the epoxy provides encapsulation and structural support. This composite approach allows large area mounting while minimizing warpage through the complementary properties of the materials
2Reliability
If glass base layer is used to reduce warpage, then warpage is minimized, but manufacturing complexity increases due to coplanarity requirements
Solution Approach 1:
The patent specifies a controlled thickness range for the glass base layer (50-150 μm) to achieve coplanarity with the molding layer upper surface. This parameter control simplifies manufacturing by providing clear design guidelines while maintaining the warpage minimization benefits of glass
3Strength
If epoxy molding compound is used for encapsulation, then structural support is improved, but thermal expansion mismatch worsens due to higher expansion coefficient
Solution Approach 1:
The patent applies different material properties to different layers: the glass base layer provides dimensional stability and low thermal expansion at the substrate level, while the epoxy molding compound provides structural support and encapsulation at the protective layer level. This local differentiation resolves the contradiction by assigning functions to materials based on their optimal properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively minimizes warpage and enhances the rigidity of the semiconductor package, ensuring reliable mounting and performance of multiple semiconductor devices by managing thermal expansion differences and providing a robust electrical signal path.
Implementation Method 1
a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer
Data Source
AI summary
A semiconductor package includes: a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate on the first redistribution structure, and including a base layer and a through electrode penetrating the base layer, wherein the base layer includes a first material; a molding layer at least partially surrounding the connection substrate and disposed on the first redistribution structure, wherein the molding layer includes a second material; a second redistribution structure disposed on the molding layer and the connection substrate; and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, and wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer.