Semiconductor Package Structure With Integrated Power Chips and Lower Height
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Solution Overview
Problem
The existing Quad Flat No-Lead (QFN) semiconductor package structure faces limitations in reducing package height, uses lead-containing solder paste causing environmental pollution, and experiences accuracy issues due to high temperature reflow processes.
Innovation Solution
A semiconductor package structure integrating a control chip and power chips within a single package using dielectric and conductive layers, conductive adhesive parts, and connecting elements, replacing the conventional reflow process with semiconductor processing to reduce volume, eliminate lead usage, and enhance accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If lead-containing solder paste is used to join copper sheet to chip, then strong bonding strength is achieved, but environmental pollution and health hazards occur
Solution Approach 1:
The patent changes the chemical composition parameters of the solder paste by replacing lead-containing materials with lead-free alternatives, maintaining bonding strength while eliminating environmental pollution. This involves adjusting alloy composition ratios and processing parameters to achieve equivalent or superior performance without harmful substances.
Solution Approach 2:
The patent adopts lead-free solder paste that can be disposed of without special handling requirements, eliminating the need for expensive lead waste management systems while maintaining adequate bonding performance for the application lifecycle.
2Strength
If high temperature reflow process at 380 degrees Celsius is used to join components, then strong metallurgical bonding is achieved, but component displacement occurs before all components are fixed, resulting in decreased accuracy
Solution Approach 1:
The patent applies preliminary fixation methods such as adhesive tapes or mechanical clamps to secure components in their correct positions before the reflow process begins. This preliminary action prevents displacement during heating, allowing the metallurgical bonding to occur without compromising placement accuracy.
Solution Approach 2:
The patent segments the joining process into distinct stages: first securing components in position, then applying heat for bonding. This segmentation allows each stage to be optimized independently, ensuring both accuracy and bonding strength.
3Power
If lead frame and bridging copper sheet are used in package structure, then high current bearing capacity is achieved, but package height cannot be reduced, limiting application fields
Solution Approach 1:
The patent transitions from a planar two-dimensional layout with lead frames to a three-dimensional vertical stacking architecture. Power components and signal components are arranged in different layers, with vertical interconnects replacing horizontal copper sheets, thereby reducing the horizontal footprint and overall package height while maintaining current bearing capacity through optimized vertical power paths.
Solution Approach 2:
The patent implements nested packaging where smaller components are positioned within the footprint of larger components, and multiple functional layers are stacked vertically. This nesting approach maximizes space utilization, reduces package dimensions, and maintains electrical performance by creating efficient current paths through the stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces package volume, improves electrical performance, eliminates lead-related pollution, and increases manufacturing accuracy by integrating chips and using semiconductor processes, thus addressing the limitations of the QFN package structure.
Implementation Method 1
a second conductive adhesive part, wherein the second conductive adhesive part adheres the fourth electrode layout to the lead frame
Implementation Method 2
a plurality of first conductive connecting elements electrically connected to an active surface of the control chip, a first electrode layout of the first power chip, and a third electrode layout of the second power chip
Data Source
AI summary
The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.