Semiconductor Package Redistribution Structure for Lower Inductance
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Solution Overview
Problem
As semiconductor packages become thinner and more complex, their inductance increases, and power integrity decreases, due to the complexity of redistribution patterns and reduction in horizontal layers, leading to inefficiencies in storage capacity and performance.
Innovation Solution
The semiconductor package incorporates an under-bump metal (UBM) pattern and a second redistribution pattern on a passivation layer, connecting first redistribution patterns and conductive pillars to reduce thickness and inductance, while improving power integrity by enhancing the connection between chip pads and package connection terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the number of horizontal layers of redistribution patterns is reduced to make the package thinner, then the package thickness decreases, but the inductance increases and power integrity deteriorates
Solution Approach 1:
The patent transitions from horizontal redistribution patterns to vertical conductive pillars, changing the dimensional orientation of current flow. This allows the package to be thinner horizontally while maintaining effective electrical connection through the vertical dimension, thus reducing inductance without compromising power integrity
Solution Approach 2:
The patent changes the geometric parameters of the connection structure by replacing planar patterns with three-dimensional pillars. This parameter change enables shorter current paths and lower inductance values while achieving reduced package thickness, simultaneously improving both the contradictory parameters
2Quantity of substance
If the pattern shape of redistribution patterns becomes more complicated to increase storage capacity, then the storage capacity increases, but the device complexity increases
Solution Approach 1:
The patent segments the redistribution function into multiple independent conductive pillars, each handling specific connections. This segmentation simplifies the overall pattern design by replacing complex continuous patterns with discrete, manageable pillar structures, reducing manufacturing complexity while maintaining high storage capacity
Solution Approach 2:
By moving from two-dimensional planar patterns to three-dimensional vertical pillars, the patent adds a new dimension for achieving high storage capacity. This dimensional change allows for simpler top-down patterning processes while achieving the required connection density through vertical structures
3Weight of moving object
If the package is made thinner and lightweight, then the package weight and thickness decrease, but the inductance increases
Solution Approach 1:
The patent changes the geometric parameters by introducing vertical conductive pillars with optimized dimensions and materials. This parameter change enables the package to achieve reduced weight and thickness while simultaneously reducing inductance through shorter current paths and improved connection geometry
Solution Approach 2:
The patent employs composite material structures in the conductive pillars, combining materials with different properties to achieve both weight reduction and low inductance. The composite structure allows for optimized electrical performance while maintaining mechanical strength and reducing overall package mass
Data Source
AI summary
A semiconductor package may include a semiconductor chip including a chip pad, a redistribution structure including a redistribution insulation layer on the semiconductor chip and first redistribution patterns on a surface of the redistribution insulation layer, a passivation layer covering the first redistribution patterns, an UBM pattern on the passivation layer and extending into an opening of the passivation layer, a second redistribution pattern on the UBM pattern, conductive pillars on the second redistribution pattern, and a package connection terminal on the conductive pillars. The opening in the passivation layer may vertically overlap a portion of each of the first redistribution patterns. The second redistribution pattern may connect some of the first redistribution patterns to each other. Some of the conductive pillars may be connected to one another through the second redistribution pattern. The first redistribution patterns may be connected to the chip pad.