Semiconductor Package Marking Structure for Heat Dissipation
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Solution Overview
Problem
Semiconductor packages face challenges in structural reliability and thermal characteristics due to the inclusion of marks within metal layers as they become thinner, affecting their performance and functionality.
Innovation Solution
A semiconductor package design incorporating a first molding member, a redistribution structure, a mark metal layer, and a mesh metal layer with holes, along with heat-conducting vias, to enhance structural integrity and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If marks are provided on surfaces of semiconductor packages, then product information is indicated, but structural reliability and thermal characteristics deteriorate due to reduced package thickness
Solution Approach 1:
The mark is formed on the upper surface of the mold compound rather than within internal metal layers, transitioning from a two-dimensional internal marking to a three-dimensional surface marking. This allows product information to be displayed without compromising the structural integrity and thermal characteristics of the package.
Solution Approach 2:
The mark is formed by selectively removing mold compound to expose underlying metal layers, creating a visual copy or representation of product information on the package surface without requiring additional material layers that would affect structural reliability.
2Loss of information
If marks are provided within metal layers, then product information is indicated, but thermal characteristics deteriorate due to interference with heat dissipation paths
Solution Approach 1:
The marking is relocated from internal metal layers to the upper surface of the mold compound, separating the information display function from the thermal conduction paths within the package structure, thereby maintaining effective heat dissipation.
Solution Approach 2:
The mold compound serves as an intermediary layer that allows the mark to be displayed on the package surface while maintaining the integrity of underlying metal layers and their thermal conduction functions. The mark is formed by exposing patterns within the mold compound that correspond to underlying metal structures.
3Length of moving object
If package thickness is reduced for miniaturization, then device size is decreased, but structural reliability deteriorates
Solution Approach 1:
The mark formation process utilizes the upper surface dimension of the mold compound rather than consuming internal metal layer space, allowing thin packages to maintain structural integrity while still providing product information display capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves structural reliability and thermal characteristics by allowing efficient heat dissipation and gas discharge, ensuring effective performance of semiconductor packages despite reduced thickness.
Implementation Method 1
The mesh metal layer is provided on a lower surface of the mark metal layer and includes at least one hole
Implementation Method 2
The heat-conducting via is provided on a lower surface of the mesh metal layer and physically connects the mesh metal layer and the second redistribution pattern to each other
Data Source
AI summary
A semiconductor package includes a first molding member, a redistribution structure, a mark metal layer, and a mesh metal layer. The first molding member covers at least one first semiconductor chip. The redistribution structure is provided on the first molding member and includes a redistribution pattern, an upper pad, and a redistribution insulating layer. The mark metal layer is provided on the redistribution structure. The mesh metal layer is provided on a lower surface of the mark metal layer and includes at least one hole.