Semiconductor Package Master Slave Chip Stacking
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Solution Overview
Problem
The challenge is to create a semiconductor package that can be mass-produced at low costs while maintaining a low loading factor and excellent performance, particularly when stacking multiple semiconductor chips, as existing methods like through silicon via (TSV) or chip-on-chip (CoC) are time-consuming and costly.
Innovation Solution
A semiconductor package design featuring a master chip and slave chips stacked on a substrate, connected via bonding wires and dummy pads, with a control circuit in the master chip to manage data and signal input/output, and driver circuits for delay compensation, allowing for efficient communication and low loading factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through silicon via (TSV) or chip-on-chip (CoC) is used to reduce loading factor, then loading factor is reduced, but manufacturing time increases and manufacturing cost increases
Solution Approach 1:
The invention divides the chip stacking process into two distinct methods: TSV for vertical integration within a chip and CoC for horizontal integration between chips. This segmentation allows each method to be applied where it is most effective, reducing overall manufacturing time while maintaining low loading factors.
Solution Approach 2:
The invention introduces a substrate as an intermediary component between master and slave chips. This substrate provides a platform for wire bonding connections, enabling efficient electrical interconnection without requiring complex TSV structures, thereby reducing manufacturing time and costs while maintaining low loading factors.
2Quantity of substance
If through silicon via (TSV) or chip-on-chip (CoC) is used to reduce loading factor, then loading factor is reduced, but manufacturing cost increases
Solution Approach 1:
The invention segments the chip interconnection approach into TSV for critical vertical paths and CoC for less time-sensitive connections. This selective application reduces manufacturing costs by avoiding the expensive TSV process where simpler wire bonding suffices, while still achieving low loading factors through optimized architecture.
Solution Approach 2:
The invention applies different interconnection qualities to different parts of the system: TSV is used where high-speed vertical communication is critical, while wire bonding is used for other connections. This local differentiation optimizes manufacturing cost by applying complex (and expensive) TSV only where necessary, rather than uniformly across all connections.
3Speed
If multiple semiconductor chips are stacked to satisfy high-speed operation demand, then performance is improved, but loading factor increases
Solution Approach 1:
The invention transitions from purely vertical stacking (single dimension) to a hybrid approach combining vertical TSV integration with horizontal wire bonding connections via substrate. This dimensional change allows performance improvement through multi-chip stacking while managing loading factor through distributed connection architecture.
Solution Approach 2:
The substrate acts as an intermediary that distributes electrical connections across multiple chips. By providing a common platform for wire bonding, it enables performance improvement through parallel processing across chips while managing loading factor through distributed rather than concentrated connection topology.
Data Source
AI summary
A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs.