Semiconductor Package Metal Bulk Layout for Heat Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices faces challenges with heat dissipation, as excessive temperatures can decrease the reliability and lifetime of semiconductor dies, and existing bonding methods like TLP bonding are prone to soldering void defects and inefficient heat dissipation due to the use of silicon bulks.
Innovation Solution
The integration of high thermal conductivity metal bulks bonded to semiconductor dies using a solder or metal layer, with the metal bulks positioned outside scribe lines to facilitate singulation and improve heat dissipation efficiency, reducing bonding defects and enhancing bond quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon bulk is used for heat dissipation through TLP bonding, then bonding is achieved, but soldering void defects occur and heat dissipation efficiency is poor
Solution Approach 1:
The patent changes the material parameter from silicon bulk to metal bulk (such as copper or aluminum) which has superior thermal conductivity. This parameter change resolves the contradiction by maintaining bonding capability while dramatically improving heat dissipation efficiency, as metal materials conduct heat far more effectively than silicon.
Solution Approach 2:
The patent employs a composite structure combining metal bulk with solder layer and optional underfill material. This composite approach allows the metal bulk to provide excellent heat dissipation while the solder layer ensures reliable bonding, and the underfill compensates for any bonding gaps, thereby resolving both the bonding quality and heat dissipation efficiency issues simultaneously.
2Strength
If metal layer is made thick to improve bonding, then bond strength increases, but singulation process becomes difficult
Solution Approach 1:
The patent segments the bonding structure by positioning the metal layer specifically at the periphery of the die rather than covering the entire surface. This segmentation allows the singulation blade to access and cut through the scribe line area without being obstructed by thick metal, while still providing sufficient bond strength at the critical bonding interfaces through the distributed peripheral metal structures.
Solution Approach 2:
The patent applies metal layer locally at specific regions (peripheral areas and scribe line regions) rather than uniformly across the entire die surface. This local quality approach provides bond strength where needed while leaving the scribe line areas accessible for singulation, thereby resolving the contradiction between bond strength and ease of singulation.
3Area of stationary object
If die surface is not level, then bonding area increases, but soldering void defects increase
Solution Approach 1:
The patent introduces underfill material as an intermediary substance between the die and substrate. This underfill compensates for surface non-levelness by filling gaps and voids, allowing the bonding interface to maintain good contact over a larger bonding area without creating soldering void defects, thereby resolving the contradiction between bonding area and soldering quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances heat dissipation efficiency, reduces bonding defects, and simplifies the singulation process by using metal bulks with high thermal conductivity, thereby improving the reliability and longevity of semiconductor packages.
Implementation Method 1
a solder layer and/or a metal layer are disposed to bond the one or more heat dissipation elements to the semiconductor dies
Implementation Method 2
one or more heat dissipation elements (e.g., metal bulks) with high thermal conductivity is/are bonded to semiconductor dies to improve heat dissipation efficiency
Data Source
AI summary
Disclosed are a semiconductor package and a manufacturing method of a semiconductor package. In one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, a first encapsulant, at least one heat dissipation element and a second encapsulant. The plurality of semiconductor dies are disposed on the interposer substrate. The first encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies. The at least one heat dissipation element is disposed on the plurality of semiconductor dies. The second encapsulant is disposed on the first encapsulant and surrounds the at least one heat dissipation element.