Semiconductor Package Vertical Interconnects With Metal-Coated Wire
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Solution Overview
Problem
Existing semiconductor packages face challenges in increasing the strength of vertical conductive structures while minimizing the number of processes involved in their formation, which affects the reliability and miniaturization of the packages.
Innovation Solution
A semiconductor package design that includes a first redistribution substrate with a semiconductor chip and vertical conductive structures comprising a wire covered by a metal layer, where the wire's top surface is exposed and the metal layer reinforces the wire's strength, allowing for easier height adjustment and increased reliability without complex multi-layer photoresist processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a wire is used as a vertical conductive structure, then the manufacturing process is simplified, but the strength and reliability are insufficient
Solution Approach 1:
The patent combines a wire (first material) with a metal layer (second material) to form a composite vertical conductive structure. The wire provides structural framework and electrical conductivity, while the metal layer coating the wire's side surface enhances strength, reliability, and heat dissipation performance, resolving the contradiction between manufacturing simplicity and structural strength.
2Temperature
If the chip thickness is increased for heat dissipation, then the heat dissipation performance is improved, but the package height increases
Solution Approach 1:
The patent applies local quality enhancement by coating only the side surface of the wire with metal layer, rather than uniformly increasing the chip thickness. This localized reinforcement improves heat dissipation along the vertical conductive path without proportionally increasing the overall package height, as the metal layer is applied selectively where thermal conduction is most needed.
3Manufacturing precision
If multiple photoresist processes are used to form vertical conductive structures, then the manufacturing precision is improved, but the number of processes and complexity increase
Solution Approach 1:
The patent extracts the complex multi-step photoresist patterning process and replaces it with a simpler wire bonding process followed by metal layer deposition. The wire is first formed using established wire bonding technology, then the metal layer is applied to the wire's side surface, eliminating the need for multiple photoresist coating, patterning, and etching steps while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the strength and reliability of the vertical conductive structures, enabling increased chip thickness for improved heat dissipation while reducing manufacturing complexity and cost by using a wire and metal layer combination, thus improving the overall semiconductor package performance.
Implementation Method 1
a metal layer covering a side surface of the wire
Data Source
AI summary
A semiconductor package includes a first redistribution substrate, a semiconductor chip on the first redistribution substrate, and vertical conductive structures spaced apart from a side surface of the semiconductor chip. Each of the vertical conductive structures includes a wire, and a metal layer covering a side surface of the wire. A top surface of the wire is exposed from the metal layer.