Semiconductor Package Layout for Thin Metal Layer Integration
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Solution Overview
Problem
The lamination of a metal layer on the wiring layer with a semiconductor device in between results in an increase in the dimensions of the semiconductor device, hindering further miniaturization and functional diversification.
Innovation Solution
A semiconductor device configuration with a specific arrangement of wiring layers, semiconductor elements, metal layers, and sealing resins, including conductive paths and protective layers, which minimizes the dimension in the direction of metal layer lamination by eliminating space between semiconductor elements and metal layers, and optimizing resin dimensions through grinding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a metal layer is laminated on the wiring layer with a semiconductor device in between, then functional diversification is achieved, but the dimension of the semiconductor device increases
Solution Approach 1:
The patent applies nesting by placing the metal layer within the sealing resin structure rather than as a separate external layer. The metal layer is embedded in the sealing resin that already encapsulates the semiconductor device, allowing the metal layer to occupy space that would otherwise be empty or filled with additional protective layers, thus adding functionality without increasing the overall device dimension.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional integrated structure by laminating the metal layer on the side surface of the semiconductor device within the sealing resin. This vertical integration within the existing depth of the sealing resin allows functional diversification while maintaining compact dimensional footprint.
2Reliability
If a metal layer is laminated on the wiring layer with a semiconductor device in between, then the metal layer can serve as conductive path, but excessive dimensional expansion occurs
Solution Approach 1:
The sealing resin serves multiple functions: it provides mechanical protection, electrical insulation, and structural support for the laminated metal layer. The metal layer itself serves dual purposes as both a conductive path for electrical connections and a structural element integrated into the sealing resin matrix, eliminating the need for separate protective or structural layers.
3Length of stationary object
If the metal layer is positioned close to the semiconductor element, then dimensional expansion is reduced, but adhesion and bonding strength must be maintained
Solution Approach 1:
The patent introduces an intermediary layer between the metal layer and the semiconductor element to ensure proper adhesion and bonding strength. This intermediary layer acts as a buffer that maintains strong bonding while allowing the metal layer to be positioned close to the semiconductor element, thus reducing dimensional expansion while maintaining bonding integrity.
4Length of stationary object
If the resin dimensions are minimized through grinding, then miniaturization is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary grinding of the resin dimensions early in the manufacturing process, before final assembly and packaging. By minimizing the resin dimensions through grinding before subsequent steps, the patent enables miniaturization while managing manufacturing complexity through process sequencing and integration.
Data Source
AI summary
A semiconductor device includes a first wiring layer, a semiconductor element conductively bonded to the first wiring layer, a second wiring layer positioned on a same side in a first direction as the first wiring layer with respect to the semiconductor element, a pillar connected and conductively bonded to the second wiring layer, and a metal layer positioned on a side opposite to the first wiring layer and the second wiring layer with respect to the semiconductor element, and connected to and electrically conductive with the pillar. The second wiring layer is spaced apart from the first wiring layer. The semiconductor element has an upper surface facing the metal layer. The metal layer is in contact with the upper surface.