Thermally Enhanced Semiconductor Package with Mold Compound

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Solution Overview

Problem

High-performance semiconductor dies generate significant heat, and existing semiconductor packages struggle with heat dissipation and harmonic distortions due to silicon on insulator (SOI) structures, limiting their use in radio-frequency applications.

Innovation Solution

A thermally enhanced semiconductor package design incorporating a thinned flip chip die with a thermally enhanced mold compound component, featuring a lower region with high thermal conductivity particulates and an upper region with lower thermal conductivity, which improves heat dissipation and reduces harmonic distortions by eliminating the silicon handle layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-performance semiconductor dies with dense transistor integration are used, then processing speed and performance are improved, but heat generation increases significantly

Engineering Contradiction:

Improveprocessing speedVSAvoidheat generation

Core Design Contradiction:

SpeedVSTemperature

Solution Approach 1:

The mold compound is divided into two distinct regions: a first mold compound region with standard thermal properties and a second mold compound region with enhanced thermal conductivity. This segmentation allows heat to be dissipated more effectively from the semiconductor die without requiring a complete redesign of the entire package structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second mold compound region is specifically positioned adjacent to the semiconductor die where heat generation is most intense. This region contains thermally conductive particles (such as aluminum oxide, aluminum nitride, or boron nitride) that create a localized thermal pathway, concentrating thermal management resources where they are most needed while maintaining other package regions at standard specifications.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If silicon on insulator (SOI) structures are used in semiconductor fabrication, then manufacturing cost is reduced and production capacity is increased, but harmonic generations and intermodulation distortions occur

Engineering Contradiction:

Improvemanufacturing cost and production capacityVSAvoidharmonic generations and intermodulation distortions

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The silicon handle layer, which causes harmonic generations and intermodulation distortions when present as SOI structure, is completely removed from the semiconductor die. This extraction eliminates the harmful RF effects while the die remains functional through alternative support structures. The removal creates a cavity space that is subsequently filled with thermally conductive mold compound material.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The removal of the silicon handle layer, which eliminates harmful harmonic generations, also creates additional cavity space within the package. This extra space is beneficially utilized to accommodate thermally conductive particles and enhance the thermal management capability of the package, converting what was previously a harmful structural element into an opportunity for improved thermal performance.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively enhances thermal performance and reduces harmonic distortions, allowing for better heat dissipation and improved radio-frequency properties by utilizing high thermal conductivity materials and eliminating silicon handle layer-related issues.

Implementation Method 1

The lower portion is filled with a second mold compound and includes a first average thermal conductivity that is at least 1.2 times greater than a second average thermal conductivity of the upper portion

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10262915B2Thermally enhanced semiconductor package with thermal additive and process for making the same

Publication Date: 2019.04.16 QORVO US INC

AI summary

The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.