Semiconductor Package Mold Layer Through-Hole Underfill
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Solution Overview
Problem
The yield of semiconductor packages manufactured by stacking multiple chips is relatively low compared to single-chip packages, and there is a need for techniques that enhance the reliability and miniaturization of high-density devices while reducing failure rates.
Innovation Solution
A semiconductor package design featuring a stack of chips with a first substrate, a semiconductor chip, a mold layer with through-holes, a second substrate, connection terminals, and an underfill resin layer that fills the through-holes and supports the connection terminals, providing electrical connectivity and stress relief between substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to achieve high-density packaging, then the device density and functionality are improved, but the manufacturing yield and reliability deteriorate
Solution Approach 1:
The patent divides the stacked package structure into separate testable units by introducing mold layers with through-holes between chips. Each chip can be individually tested and accessed through the mold layer, allowing segmentation of the testing process while maintaining the high-density stacked configuration.
Solution Approach 2:
The mold layer with through-holes acts as an intermediary structure that enables testing and electrical access to individual chips within the stacked configuration. This intermediary layer allows test probes to reach connection terminals without requiring complete disassembly of the stack, thereby maintaining reliability while achieving high density.
2Area of stationary object
If multiple semiconductor chips are stacked to achieve miniaturization, then the footprint area is reduced, but the stress on connection terminals increases
Solution Approach 1:
The mold layer is designed with through-holes that provide stress relief pathways before excessive stress can damage the connection terminals. The structure anticipates and cushions the thermal and mechanical stress that arises during operation, preventing crack propagation while maintaining the miniaturized stacked configuration.
3Reliability
If connection terminals are placed in through-holes of mold layer for electrical connectivity, then the electrical connection is improved, but the structural complexity increases
Solution Approach 1:
The mold layer serves multiple functions simultaneously: it provides structural support for the stacked chips, creates through-holes for electrical access to connection terminals, and acts as a barrier layer for stress management. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in structural complexity while improving electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the yield and reliability of high-density semiconductor packages by enhancing connectivity and reducing stress on connection terminals, thereby preventing cracks and ensuring efficient miniaturization and multi-functionality in electronic devices.
Implementation Method 1
an underfill resin layer occupying a region between the semiconductor chip and the second substrate and extending contiguously from said region into the through-hole
Data Source
AI summary
A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.