3D Semiconductor Package Layout With Mold Vias for Compact Reliability
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in reducing the size and weight of high-frequency semiconductor components while maintaining good electrical characteristics, which is essential for compact portable electronic devices.
Innovation Solution
A semiconductor package design that includes a redistribution substrate with stacked insulating layers and redistribution patterns, a first and second semiconductor chip, a third semiconductor chip, molding portions, bump patterns, and a mold via that electrically connects the semiconductor chips to the redistribution substrate, allowing for reduced size and improved reliability by integrating multiple chips in a single package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are integrated in a single package to reduce size, then the package size and weight are reduced, but the electrical characteristics and reliability may deteriorate
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked configuration, placing chips at different vertical levels (first chip on first surface, second chip on second surface, third chip in between) to achieve compact integration while maintaining electrical performance through vertical interconnection via mold vias and redistribution patterns
Solution Approach 2:
The patent introduces mold vias as intermediary conductive elements that penetrate the molding compound to establish electrical connections between chips at different levels and the redistribution substrate, enabling reliable signal transmission through the three-dimensional package structure
2Volume of moving object
If multiple semiconductor chips are integrated in a single package to reduce size, then the package size is reduced, but the fabrication process complexity increases
Solution Approach 1:
The patent combines multiple chips, molding portions, and redistribution patterns into a single integrated package structure, where the molding compound serves dual purposes as both encapsulation material and medium for forming mold vias, simplifying the overall fabrication process despite the three-dimensional complexity
Data Source
AI summary
A semiconductor package may include a redistribution substrate including first and second surfaces opposite each other, a first semiconductor chip on the first surface, a first molding portion on a side surface of the first semiconductor chip, a second semiconductor chip between the first semiconductor chip and the redistribution substrate, a second molding portion between the redistribution substrate and the first molding portion and on a side surface of the second semiconductor chip, bump patterns between the second semiconductor chip and the redistribution substrate, and a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate. The redistribution substrate may include first and second redistribution patterns sequentially in an insulating layer. The mold via may contact the second redistribution pattern, and the bump patterns may contact the first redistribution pattern.