Semiconductor Package With Integrated Molding Layer Trench
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved electrical characteristics and compact size while maintaining manufacturing cost-effectiveness.
Innovation Solution
The semiconductor package design includes a substrate with a trench and through hole structure, a semiconductor chip, a capacitor chip, and a molding layer that extends vertically through the substrate, providing electrical connections and encapsulation, which reduces noise and allows for a compact form factor without the need for a separate under-fill process, thereby lowering manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate under-fill process is used to encapsulate the capacitor chip, then the reliability and protection of the capacitor chip is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the under-fill encapsulation function with the existing molding layer structure. The molding layer is extended to cover the capacitor chip in the trench, eliminating the need for a separate under-fill process. This integration maintains capacitor chip protection while simplifying the manufacturing process by reducing the number of discrete steps and materials required.
Solution Approach 2:
The molding layer is designed to serve multiple functions simultaneously: it provides encapsulation for the semiconductor chip, fills the through hole for electrical connection, and extends to cover the capacitor chip in the trench. This multi-functional design eliminates the need for separate under-fill material and process, reducing manufacturing complexity while maintaining reliability.
2Reliability
If the molding layer is extended vertically through the substrate to provide electrical connections, then the electrical characteristics and signal noise are improved, but the device complexity increases
Solution Approach 1:
The molding layer is designed to perform multiple functions: it provides mechanical encapsulation, establishes electrical connections through the through hole, and reduces signal noise. By making the molding layer multi-functional rather than requiring separate components for each function, the patent improves electrical characteristics without proportionally increasing device complexity.
Solution Approach 2:
The molding layer structure is nested within the substrate architecture, with the molding layer extending into the through hole and covering the capacitor chip in the trench. This nested configuration allows the molding layer to provide electrical connections and noise reduction without requiring additional external structures, thereby improving electrical characteristics while managing complexity through efficient spatial integration.
3Volume of moving object
If the capacitor chip is placed in a trench on the substrate, then the compact size is achieved, but the manufacturing precision requirements increase
Solution Approach 1:
The trench is formed in the substrate before the capacitor chip is mounted. This preliminary action allows for precise trench formation using standard substrate processing techniques, and the subsequent capacitor chip placement can be performed with normal precision alignment. By preparing the trench structure in advance, the patent achieves compact packaging without excessively increasing the precision requirements for the final assembly step.
Data Source
AI summary
A semiconductor package includes a first substrate that includes a first trench on a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench, a first semiconductor chip on the first substrate, a first capacitor chip in the first trench and on the first substrate, and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer includes a first part that extends parallel to a top surface of the first substrate, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part is coplanar with the bottom surface of the first substrate.