Stacked Semiconductor Package Molding Layer Trench Design
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Solution Overview
Problem
Current semiconductor packages face challenges in improving process yield and reliability due to limitations in packaging processes, particularly in withstanding external impacts and stress.
Innovation Solution
A semiconductor package design featuring a stacked chip configuration with multiple semiconductor chips and a molding layer structure that extends from the interposer's upper surface to a trench, providing enhanced protection and reliability by distributing external stress effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional molding layer structure is used, then the manufacturing process is simple, but the package cannot withstand external impacts and stress effectively
Solution Approach 1:
The molding layer is divided into multiple distinct layers: a first molding layer that fills the trench and surrounds chip side surfaces, and a second molding layer that covers the first molding layer and extends to the upper surface of the interposer. This segmentation allows each layer to perform specific functions - the first layer provides stress distribution and structural support, while the second layer provides protection and planarity, thereby improving reliability without excessive complexity
Solution Approach 2:
The molding layers extend in multiple dimensions - vertically filling the trench and covering chip surfaces, and horizontally extending to the interposer upper surface. This multi-dimensional coverage ensures comprehensive protection against external impacts from various directions and effective stress distribution throughout the package structure
2Reliability
If the molding layer extends deeply into the trench, then stress distribution improves, but warpage increases
Solution Approach 1:
The first molding layer is selectively applied to fill the trench and surround the side surfaces of the stacked chips, providing localized stress distribution exactly where needed. The second molding layer is then applied to cover the first layer and extend to the interposer upper surface, providing overall protection. This localized application approach improves stress distribution without causing excessive warpage that would result from uniform deep extension throughout the entire structure
3Productivity
If multiple stacked chips are used, then integration increases, but process yield decreases
Solution Approach 1:
The molding layers are formed to completely surround and protect the stacked chips before final packaging operations. The first molding layer fills the trench and surrounds chip side surfaces, while the second molding layer provides additional coverage. This preliminary protective action prevents damage during subsequent handling and assembly processes, thereby maintaining high process yield even with multiple stacked chips
Solution Approach 2:
The molding layers act as a cushioning structure that absorbs and distributes external stresses before they can reach the stacked chips. By providing this protective barrier in advance, the package structure prevents stress concentration on individual chips, reducing the risk of failure and maintaining high process yield during integration
Data Source
AI summary
A semiconductor package includes an interposer; a first stacked chip including a first semiconductor chip disposed on the interposer and one or more second semiconductor chips disposed on the first semiconductor chip; a first molding layer surrounding the first stacked chip; and a second molding layer surrounding the first molding layer, wherein the second molding layer extends from an uppermost surface of the interposer to a trench of the interposer.