Semiconductor Package Warpage Reduction via Asymmetric Molding
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Solution Overview
Problem
Semiconductor device packages with stacked electronic devices are prone to warpage due to asymmetrical structures and mismatched physical characteristics, leading to insufficient robustness.
Innovation Solution
A semiconductor device package design that includes a package substrate, first and second electronic devices, and a first molding layer, where the molding layer encapsulates the package substrate's edge and surface, with controlled thickness ratios and material properties to minimize warpage and enhance robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If stacked electronic devices are arranged in an asymmetrical structure to increase integration density, then device functionality and integration are improved, but warpage occurs due to mismatched physical characteristics between adjacent layers
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing an asymmetrical molding layer structure where the first molding layer has a different thickness than the second molding layer. The first molding layer thickness is specifically controlled to be 0.5 to 2 times the package substrate thickness, creating an asymmetrical compensation structure that counteracts the warpage caused by the asymmetrical stacked device configuration. This asymmetrical molding layer distribution balances the stress distribution across the package substrate.
Solution Approach 2:
The patent employs parameter changes by precisely controlling the thickness parameters of the molding layers relative to the package substrate. The first molding layer thickness is set within a specific range (0.5 to 2 times the substrate thickness), and the second molding layer thickness is set within another specific range (0.1 to 0.5 times the substrate thickness). These controlled parameter variations optimize the stress distribution to minimize warpage while maintaining the asymmetrical stacked device structure.
2Reliability
If the molding layer thickness is increased to provide better encapsulation and protection, then robustness is improved, but warpage is exacerbated due to mismatched CTE and Young's modulus between layers
Solution Approach 1:
The patent applies local quality principle by providing different molding layer thicknesses at different locations of the package substrate. The first molding layer has a greater thickness (0.5 to 2 times substrate thickness) compared to the second molding layer (0.1 to 0.5 times substrate thickness). This localized variation in molding layer quality provides enhanced protection where needed while simultaneously using the thickness differential to compensate for warpage caused by CTE and Young's modulus mismatches between the stacked devices and substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage to less than 8 mils and enhances the robustness of the semiconductor device package by using a molding layer with specific thickness and material properties, such as CTE and Young's modulus, to alleviate thermal expansion and mechanical stress.
Implementation Method 1
a molding layer with specific thickness and material properties, such as CTE and Young's modulus, to alleviate thermal expansion and mechanical stress
Implementation Method 2
a molding layer with specific thickness and material properties, such as CTE and Young's modulus, to alleviate thermal expansion and mechanical stress
Data Source
AI summary
A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.