Semiconductor Package Shielding Structure to Prevent Mounting Shorts
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Solution Overview
Problem
Existing semiconductor packages face challenges in preventing shorting with adjacent conductive patterns during mounting, which affects their reliability and durability.
Innovation Solution
A semiconductor package design featuring a capping insulation layer with a laterally protruding capping protrusion and a shielding layer, where the capping insulation layer has a first and second capping sidewall with varying surface roughness, and the shielding layer has a similar structure, preventing undesirable contact with adjacent conductive patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor package structure is used, then the manufacturing process is simple, but shorting with adjacent conductive patterns occurs during mounting
Solution Approach 1:
An insulation layer is introduced as an intermediary component between the semiconductor chip and adjacent conductive patterns. This insulation layer extends laterally beyond the chip edges to provide electrical isolation, preventing shorting while maintaining a relatively simple overall package structure.
Solution Approach 2:
The insulation structure is extended into the lateral dimension beyond the chip boundaries. By adding lateral extension in the horizontal plane, the patent achieves electrical isolation without increasing vertical height or complicating the basic package architecture.
2Reliability
If the capping insulation layer has uniform surface roughness, then the manufacturing process is simple, but mounting quality is insufficient
Solution Approach 1:
The capping insulation layer is designed with non-uniform surface roughness distribution: the first surface has lower roughness for smooth operation, while the second surface has higher roughness to enhance adhesion to the mounting substrate. This local differentiation of surface properties improves mounting quality without requiring complex manufacturing processes.
Data Source
AI summary
A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.