Semiconductor Package Design for Multi-Die Integration
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Solution Overview
Problem
The challenge in semiconductor device assembly is to effectively interconnect multiple types of chips within a small footprint, as conventional methods struggle with varying electrical connections and the complexity of packaging three or more different types of dies, such as high-speed serial memory, low-speed wide memory, and processors, while minimizing signal delay and reducing package size.
Innovation Solution
A semiconductor package design that includes multiple die types, utilizing different types of electrical connections, such as bond wires, flip-chip connections, through-substrate vias, and copper pillars, to facilitate efficient data pathways between high-speed serial memory, low-speed wide memory, and processors within a chip-scale package footprint, allowing for a dense and compact package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple different types of chips are interconnected within a small footprint, then device functionality and integration density are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the interconnection system into multiple specialized substrates, each optimized for specific connection types. First substrate handles bond wire connections to high-speed serial memory, while second substrate handles flip-chip connections to low-speed wide memory and processor. This segmentation allows each substrate to be optimized independently, reducing overall complexity despite high functionality.
Solution Approach 2:
The patent introduces intermediate substrates that act as mediators between different memory types and the processor. These substrates provide standardized interface layers that simplify the interconnection architecture, allowing different connection technologies (bond wire, flip-chip) to be integrated without creating excessive complexity in the overall system.
2Reliability
If different types of electrical connections are used for different memory types, then electrical connection performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the assembly into separate substrates, each dedicated to specific connection types. First substrate is optimized for bond wire connections to high-speed serial memory, while second substrate is optimized for flip-chip connections to low-speed wide memory and processor. This segmentation allows each substrate to be manufactured and tested independently with precision optimized for its specific connection type, rather than requiring all components to meet all precision requirements simultaneously.
Solution Approach 2:
The patent performs preliminary assembly and testing of each substrate independently before final integration. Each substrate is prepared with its specific connection type (bond wire or flip-chip) and tested for functionality before being combined with other substrates. This preliminary action ensures that manufacturing precision requirements are met for each connection type without compounding difficulties during final assembly.
3Area of stationary object
If three or more different types of dies are packaged together, then area efficiency is improved, but package complexity increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. Multiple substrates and dies are arranged in vertical layers, with first substrate containing high-speed serial memory, second substrate containing low-speed wide memory and processor, and additional substrates providing interconnection layers. This vertical stacking achieves high integration density (three or more die types in chip-scale footprint) while managing complexity through layered modular design, where each layer has specialized functions and standardized interfaces.
4Loss of time
If short electrical connections are used between processor and memory, then signal delay is reduced, but manufacturing difficulty increases
Solution Approach 1:
The patent segments the system into closely spaced vertical layers with short inter-layer connections. The processor and memory dies are mounted on adjacent substrates with minimal lateral separation, and electrical connections are made through vertical vias and interconnect layers rather than long lateral traces. This segmented layered architecture achieves short signal paths (reduced delay) while maintaining manufacturability through standardized via and interconnect processes used in multi-layer PCB and substrate fabrication.
Data Source
AI summary
A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.