Semiconductor Package Layout for Multi-Chip Integration
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Solution Overview
Problem
The increasing demand for high-performance, small, and light electronic components in the electronics industry poses challenges in integrating multiple semiconductor chips effectively, leading to issues with adhesive members and component size reduction.
Innovation Solution
A semiconductor package design incorporating a redistribution substrate, connection substrate, interposer substrate, and molding layers to electrically connect and integrate multiple semiconductor chips, with through electrodes and molding layers enhancing electrical contact and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple adhesive members are used to adhere multiple semiconductor chips to each other, then the integration of multiple chips is achieved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple adhesive members into a single adhesive layer that simultaneously bonds multiple semiconductor chips to the substrate. This single adhesive layer performs the function of multiple separate adhesive members, reducing structural complexity while maintaining the integration of multiple chips. The adhesive layer is applied as a continuous or discontinuous coating that adheres multiple chips in a stacked or side-by-side configuration without requiring individual adhesive members for each chip.
2Adaptability or versatility
If multiple adhesive members are used to adhere multiple semiconductor chips to each other, then the integration of multiple chips is achieved, but the productivity decreases
Solution Approach 1:
The patent applies adhesive members or adhesive layer in advance before mounting the semiconductor chips onto the substrate. This preliminary application of adhesive allows for more efficient assembly processes, as the adhesive is already in place to receive the chips during subsequent mounting operations. This approach eliminates the need for complex multi-step adhesive application processes during chip assembly, thereby improving manufacturing productivity.
3Weight of moving object
If the size of individual semiconductor components is reduced to create small and light electronic components, then the portability is improved, but the integration density and electrical connection reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple chips are arranged vertically in layers rather than spread out horizontally, enabling compact integration while maintaining reliable electrical connections through vertical interconnect structures. This dimensional change allows small, lightweight components to achieve high integration density without compromising connection reliability, as the stacked architecture reduces the overall package size and weight while maintaining robust electrical pathways between chips and substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the integration and productivity of semiconductor packages by enabling efficient electrical connection and alignment of multiple semiconductor chips, reducing the need for excessive adhesive members and enhancing the compactness of electronic components.
Implementation Method 1
a first interposer substrate including a through electrode extending through the first interposer substrate disposed in the opening of the connection substrate and on the first redistribution substrate
Implementation Method 2
a first molding layer on the chip structure, the first interposer substrate, and the second semiconductor chip in the opening of the connection substrate
Data Source
AI summary
A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate, wherein the connection substrate includes an opening extending through the connection substrate, a chip structure including a first semiconductor chip in the opening and on the first redistribution substrate, a first interposer substrate including a through electrode extending through the first interposer substrate in the opening and on the first redistribution substrate, wherein the first interposer substrate is spaced apart from the chip structure, a second semiconductor chip on the first interposer substrate and electrically connected to the through electrode, a first molding layer on the chip structure, first interposer substrate, and second semiconductor chip, and a second redistribution substrate on the first molding layer and connection substrate, wherein a lower surface of the chip structure and the first interposer substrate are in electrical contact with an upper surface of the first redistribution substrate.