Semiconductor Package Stacking Without TSVs Using Redistribution Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing through-silicon via (TSV) process for stacking semiconductor devices is complex and expensive, making it challenging to achieve compactness and excellent electrical characteristics in high-frequency semiconductor packages.
Innovation Solution
A semiconductor package design that includes a package substrate with a first semiconductor chip, a molding layer, a redistribution layer, and through electrodes, allowing for flip-chip mounting of additional semiconductor chips without penetrating vias, reducing manufacturing costs and increasing electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon via (TSV) process is used for stacking semiconductor devices, then vertical interconnect access is achieved, but the process becomes complex and excessively expensive
Solution Approach 1:
The patent divides the interconnection structure into multiple layers: a first molding layer surrounding the first semiconductor chip, a first redistribution layer on the first molding layer, and a second molding layer surrounding the second semiconductor chip. This segmentation eliminates the need for through-silicon vias while achieving vertical interconnect access through a simplified multi-layer structure.
Solution Approach 2:
The first molding layer and first redistribution layer serve as intermediary structures between the first semiconductor chip and the second semiconductor chip. Instead of creating direct vertical connections through the chip (TSV), the patent uses these intermediary layers to establish electrical connections, thereby simplifying the manufacturing process.
2Reliability
If through-silicon via (TSV) process is used for stacking semiconductor devices, then vertical interconnect access is achieved, but manufacturing cost increases excessively
Solution Approach 1:
The patent divides the interconnection structure into multiple layers: a first molding layer surrounding the first semiconductor chip, a first redistribution layer on the first molding layer, and a second molding layer surrounding the second semiconductor chip. This segmentation eliminates the need for through-silicon vias while achieving vertical interconnect access through a simplified multi-layer structure.
Solution Approach 2:
The patent replaces the expensive and complex TSV process with a more cost-effective approach using standard molding and redistribution layer fabrication. The molding layers and redistribution layers serve as disposable intermediary structures that enable vertical interconnection without requiring costly through-silicon via formation processes.
3Volume of moving object
If multiple semiconductor chips are integrated into a single package, then size and weight of electronic parts are reduced, but wiring area requirements increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical stacking. By stacking the first semiconductor chip and second semiconductor chip vertically with molding layers and redistribution layers in between, the design utilizes the vertical dimension to reduce the horizontal wiring area while maintaining compact package size.
Solution Approach 2:
The patent employs a nested structure where the first molding layer surrounds the first semiconductor chip, the first redistribution layer is positioned on the first molding layer, and the second molding layer surrounds the second semiconductor chip. This nested arrangement efficiently utilizes space, reducing the overall wiring area while accommodating multiple chips in a compact configuration.
Data Source
AI summary
A semiconductor package includes a package substrate, a first chip structure mounted on the package substrate, a first semiconductor chip mounted on the first chip structure, and a first molding layer that surrounds the first chip structure and the first semiconductor chip on the package substrate. The first chip structure includes a second semiconductor chip, a second molding layer on a lateral surface of the second semiconductor chip, a first redistribution layer on the second semiconductor chip and the second molding layer, and a first through electrode on a side of the second semiconductor chip and connected to the first redistribution layer.