Semiconductor Package Non-Contact Bridge Chip Proximity Communication
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Solution Overview
Problem
Conventional semiconductor packages face issues with warpage due to thermal expansion mismatch and precise alignment challenges, leading to low yield rates and the need for underfill materials.
Innovation Solution
A semiconductor package design featuring a silicon substrate with vias and bridge chips, where active chips are mounted above bridge chips without physical contact, enabling proximity communication and eliminating the need for underfill, thus addressing thermal expansion mismatch and alignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an organic substrate is used to bond active chips and bridge chips, then the chips can be electrically connected and proximately communicated, but the package warps easily due to CTE mismatch between the organic substrate and chips
Solution Approach 1:
The patent changes the substrate material from organic to silicon, which has a CTE that closely matches that of the active chips and bridge chips. This parameter change in material composition resolves the CTE mismatch issue, eliminating warpage while maintaining electrical connection and proximity communication functionality.
2Reliability
If conventional bonding methods are used to attach chips to the substrate, then electrical connection is achieved, but precise alignment between chips is difficult and yield rate is low
Solution Approach 1:
The patent introduces a silicon substrate with precisely positioned vias as an intermediary structure. These vias serve as alignment references that enable precise positioning of the active chips and bridge chips, significantly improving alignment precision and yield rate while ensuring reliable electrical connection.
3Stability of the object's composition
If underfill material is applied between chips and substrate to prevent warpage, then structural stability is improved, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The patent extracts and eliminates the underfill material from the package structure by using a silicon substrate that inherently prevents warpage through CTE matching. This removal of the underfill step simplifies the manufacturing process, reduces complexity, and decreases production time while maintaining structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor package with improved thermal stability, high yield rates, and precise alignment, eliminating the need for underfill and reducing warpage concerns.
Implementation Method 1
the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip
Data Source
AI summary
The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.