Semiconductor Package Non-Coplanar Encapsulant Yield
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Solution Overview
Problem
The high cost of fan-out processes in semiconductor packaging is increased due to the expense of high-end semiconductor dies and the low yield of fine-line redistribution layers, leading to yield loss and waste of expensive dies.
Innovation Solution
A semiconductor package structure is developed with a known good conductive structure including a fine-line redistribution layer attached to a high-end semiconductor die, and a method for manufacturing this structure involves forming a base wiring structure, singulating it into conductive structures, and attaching semiconductor components with a non-coplanar encapsulant to reduce costs and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fine-line redistribution layer is formed on the encapsulant to electrically connect high-end and low-end semiconductor dies, then electrical connectivity between dies is achieved, but the yield loss increases due to the expensive high-end dies being wasted
Solution Approach 1:
The patent forms the redistribution layer on the encapsulant before mounting the semiconductor dies. This preliminary action allows the RDL to be pre-configured with proper electrical pathways, and any defects can be detected and corrected before the expensive dies are mounted, preventing yield loss while ensuring reliable electrical connectivity.
Solution Approach 2:
The patent divides the redistribution layer formation process into separate stages: first forming the RDL on the encapsulant, then mounting the dies separately. This segmentation allows independent optimization and quality control of each step, reducing the risk that RDL defects will cause waste of expensive dies.
2Reliability
If high-end semiconductor dies are used in the fan-out process, then package performance is improved, but the manufacturing cost increases
Solution Approach 1:
The patent uses the encapsulant itself as the substrate for forming the redistribution layer, eliminating the need for separate expensive interposer substrates. The encapsulant serves multiple functions: mechanical support, electrical insulation, and RDL formation surface, thereby reducing overall manufacturing cost while maintaining package performance.
3Reliability
If the redistribution layer is formed after die mounting, then electrical connection is achieved, but the process complexity and cost increase due to rework requirements
Solution Approach 1:
The patent performs the redistribution layer formation as a preliminary step before die mounting. This eliminates the need for complex post-mounting processes such as substrate thinning, RDL formation, and re-bumping, significantly reducing process complexity while ensuring reliable electrical connections.
Data Source
AI summary
A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.