Semiconductor Package Notch Structure for Photonic Waveguide Protection

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Solution Overview

Problem

The optical waveguide layer of photonic integrated circuit chips is easily damaged during the manufacturing process of semiconductor packaging, particularly due to participation in multiple manufacturing steps such as heating and alkali cleaning, which affects their integrity and functionality.

Innovation Solution

A semiconductor package design featuring a carrier plate with a notch that houses the photonic integrated circuit chip, allowing it to be manufactured individually and assembled separately from the electronic integrated circuit chip, thereby avoiding damaging processes and ensuring the integrity of the optical waveguide layer. This design uses an interposer substrate to electrically connect both chips, facilitating high-density integration and optical coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the photonic integrated circuit chip participates in multiple manufacturing steps (heating, alkali cleaning) during semiconductor packaging, then the manufacturing process can be simplified and productivity improved, but the optical waveguide layer is easily damaged

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidintegrity of optical waveguide layer
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the manufacturing process into separate stages: the photonic integrated circuit chip is manufactured and protected separately, then integrated into the semiconductor package later. This segmentation allows the photonic chip to avoid damaging manufacturing steps while maintaining manufacturing efficiency for other components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The photonic integrated circuit chip is manufactured and its optical waveguide layer is protected in advance before the semiconductor packaging process begins. This preliminary action ensures the optical components are already formed and protected before exposure to potentially damaging manufacturing conditions.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the photonic integrated circuit chip is manufactured individually and assembled separately, then the optical waveguide layer is protected from damage, but the device complexity increases

Engineering Contradiction:
Improveintegrity of optical waveguide layerVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary structure (the carrier substrate with recess) that facilitates the separate manufacturing and integration of the photonic chip. This intermediary simplifies the assembly process by providing a pre-designed interface and positioning mechanism, reducing overall process complexity despite separate manufacturing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If the photonic integrated circuit chip is disposed in a notch of the carrier plate, then the optical waveguide layer is protected and diverse manufacturing requirements are met, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveflexibility for diverse manufacturing requirementsVSAvoidpositioning precision of photonic chip
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a specific recess structure in the carrier substrate at the precise location where the photonic chip needs to be positioned. This localized structural feature provides both protection and positioning guidance, reducing overall precision requirements while maintaining adaptability for different manufacturing scenarios.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250105230A1Semiconductor package and manufacturing method thereof
Publication Date: 2025.03.27 IND TECH RES INST
  • US20250105230A1 patent drawing
  • US20250105230A1 patent drawing
  • US20250105230A1 patent drawing

AI summary

A semiconductor package includes a carrier plate, a photonic integrated circuit chip, an electronic integrated circuit chip and an interposer substrate. The carrier plate has a notch and a first surface and a second surfaces opposite to the first surface, and the notch extends from the first surface toward the second surface. The photonic integrated circuit chip is disposed within the notch. The electronic integrated circuit chip is disposed on the first surface of the carrier plate. The photonic integrated circuit chip and the electronic integrated circuit chip are disposed on the carrier through the interposer substrate.