Semiconductor Package Opening Layout for Reliable Wire Bonding

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Solution Overview

Problem

The flip chip bonding process for semiconductor packages is not cost-effective compared to other bonding techniques, and it lacks efficiency in connecting chips to package substrates.

Innovation Solution

A semiconductor package design featuring a package substrate with an opening that has a wider width on one side than the other, allowing bonding wires to connect I/O pads on the semiconductor die to conductive pads on the package substrate without physical contact with the opening's edges, thereby preventing damage during wire formation and enabling a more efficient face-down attachment method.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If flip chip bonding process is used to attach semiconductor die to package substrate, then connection between chip and package substrate is shortened, but manufacturing cost increases and process complexity increases

Engineering Contradiction:
Improveconnection lengthVSAvoidmanufacturing cost
Core Design Contradiction:
Length of moving objectVSEase of manufacture

Solution Approach 1:

The patent introduces bonding wires as an intermediary element to connect the semiconductor die to the package substrate. Instead of directly attaching the die in a flip chip manner, the bonding wires serve as a mediator that establishes electrical connections while allowing the die to be attached in a more cost-effective face-down manner using conventional bonding processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the connection path into two distinct parts: the physical attachment of the semiconductor die to the package substrate, and the electrical connection between I/O pads and external contacts. This segmentation allows the die to be attached using cost-effective conventional bonding while electrical connections are established separately through bonding wires passing through openings in the substrate.

Inventive Principle:
Principle #1Segmentation

2Length of moving object

If flip chip bonding process is used to attach semiconductor die to package substrate, then connection between chip and package substrate is shortened, but process complexity increases

Engineering Contradiction:
Improveconnection lengthVSAvoidprocess complexity
Core Design Contradiction:
Length of moving objectVSDevice complexity

Solution Approach 1:

The bonding wires act as an intermediary that decouples the attachment process from the electrical connection process. This allows the use of simpler, more conventional die attachment methods while achieving the electrical connection function through a separate wire bonding step, thereby reducing overall process complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of making the die contact the substrate directly through flip chip bonding, the patent inverts the approach by having the die attached face-down to the substrate and then establishing electrical connections through bonding wires that pass through openings in the substrate from the opposite side.

Inventive Principle:
Principle #13The other way round (Inversion)

3Area of stationary object

If bonding wires are placed close to opening edges to maximize I/O pad area, then available area for I/O pads increases, but risk of wire damage increases

Engineering Contradiction:
ImproveI/O pad areaVSAvoidwire formation reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies different functional zones within the opening structure: the central region accommodates bonding wires with sufficient clearance from edges for reliable formation, while the peripheral region around the opening provides space for additional I/O pads. This local differentiation of spatial quality allows both wire reliability and pad density to be optimized simultaneously.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12021017B2Semiconductor package and manufacturing method thereof
Publication Date: 2024.06.25 NAN YA TECH
  • US12021017B2 patent drawing
  • US12021017B2 patent drawing
  • US12021017B2 patent drawing

AI summary

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor die, a package substrate and bonding wires. The semiconductor die has I/O pads arranged at an active side. The package substrate is provided with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and has an opening penetrating through the package substrate. The I/O pads are overlapped with the opening. A width of the opening at the second side of the package substrate is greater than a width of the opening at the first side of the package substrate. The bonding wires connect the I/O pads to the second side of the package substrate through the opening of the package substrate.