Semiconductor Package Optical Chip Stacking with Groove Notch Alignment
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Solution Overview
Problem
Current semiconductor packages face limitations in power efficiency, data processing rate, and memory capacity, particularly in integrating optical integrated circuit chips effectively.
Innovation Solution
The semiconductor package design includes a redistribution layer with a stack structure that incorporates multiple optical integrated circuit chips, each with a notch and groove configuration for optical fiber coupling, allowing for vertical stacking and hybrid-bonding, thereby increasing the number of processing channels and improving electrical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple optical integrated circuit chips are stacked vertically, then data processing rate and memory capacity are improved, but device complexity increases
Solution Approach 1:
The optical integrated circuit chip is divided into multiple functional layers including first and second optical integrated circuit chips stacked vertically. Each chip contains distinct functional regions (first region with optical components, second region with electronic components) that are segmented to perform specific tasks in the data processing pipeline, enabling higher throughput while maintaining manageable complexity through functional decomposition.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical stacking configuration. Multiple optical integrated circuit chips are arranged in the vertical dimension (stacked in the third direction), allowing increased data processing capacity and memory capacity without expanding the horizontal footprint, thereby improving productivity while controlling device complexity through spatial optimization.
2Use of energy by moving object
If optical integrated circuit chips are stacked vertically with groove and notch configurations, then electrical paths are shortened and power efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The optical integrated circuit chip employs asymmetric groove and notch configurations positioned at specific locations (first groove and first notch in the first optical integrated circuit chip, second groove and second notch in the second optical integrated circuit chip). These asymmetric features are strategically placed to align vertically when chips are stacked, creating optimized electrical paths that reduce resistance and improve power efficiency while establishing precise alignment requirements for manufacturing.
Solution Approach 2:
The groove and notch structures serve as intermediary alignment features that facilitate precise positioning between stacked optical integrated circuit chips. These features act as mechanical guides and electrical conduits, mediating the connection between upper and lower chips to ensure proper alignment and optimized electrical paths, thereby improving power efficiency while defining specific manufacturing precision requirements for the intermediary structures.
Data Source
AI summary
A semiconductor package includes a redistribution layer on a substrate, a semiconductor chip on the redistribution layer, and a stack structure on the redistribution layer and spaced apart from the semiconductor chip in a horizontal direction, wherein the stack structure includes an optical integrated circuit chip, the first optical integrated circuit chip includes a first region adjacent to the semiconductor chip and a second region adjacent to an outer portion of the substrate, and the optical integrated circuit chip defines a first notch and a first groove in the second region, the first groove recessed upwards in a vertical direction from a lower surface of the optical integrated circuit chip, the first groove recessed downwards in the vertical direction from an upper surface of the optical integrated circuit chip.