Semiconductor Package Layout for Short EIC-PIC Optical Links

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Solution Overview

Problem

Existing semiconductor packages face challenges in reducing the signal distance between electronic integrated circuits (EICs) and photonic integrated circuits (PICs), which affects the efficiency and compactness of the packages.

Innovation Solution

The semiconductor package design includes a package substrate with a semiconductor chip and EICs, where a PIC chip is positioned on top of the EICs. The PIC chip has a larger horizontal surface area than the EICs, with a portion protruding horizontally. A reflective portion with a transparent spacer and mirrors is placed on the lower surface of the PIC chip, and an optical fiber is connected to this reflective portion, allowing for efficient signal transmission between the EICs and PICs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the PIC chip is positioned directly above the EIC chip vertically, then the horizontal signal distance is reduced, but the optical coupling efficiency deteriorates due to misalignment with the optical fiber

Engineering Contradiction:
Improvehorizontal signal distanceVSAvoidoptical coupling efficiency
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The PIC chip is designed with a protruding portion that extends beyond the EIC chip in the horizontal direction. This dimensional change allows the optical component on the PIC chip to be positioned laterally adjacent to the EIC chip while maintaining vertical alignment, thereby enabling both short horizontal signal distance and effective optical fiber coupling simultaneously

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the PIC chip has the same horizontal surface area as the EIC chip, then the package layout is compact, but the optical fiber cannot be properly positioned for effective coupling

Engineering Contradiction:
Improvehorizontal surface areaVSAvoidoptical coupling efficiency
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The PIC chip is designed with an asymmetric protruding portion that extends beyond the EIC chip's boundary. This asymmetric configuration provides the necessary space for positioning the optical component and optical fiber for effective coupling, while minimizing the additional area occupied compared to a fully larger PIC chip design

Inventive Principle:
Principle #4Asymmetry

3Manufacturing precision

If transparent spacers are used to maintain spacing between components, then alignment is improved, but the package size increases due to the spacer dimensions

Engineering Contradiction:
Improvealignment precisionVSAvoidpackage size
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

Instead of using transparent spacers that extend in the horizontal direction, the invention positions the optical component on the protruding portion of the PIC chip laterally adjacent to the EIC chip. This eliminates the need for horizontal spacers, as the vertical stacking combined with lateral positioning achieves both alignment and compactness

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces the horizontal signal distance between EICs and PICs, enhancing the efficiency and compactness of the semiconductor package while enabling effective optical signal transmission.

Implementation Method 1

a reflective portion disposed on a lower surface of the portion of the photonic integrated circuit chip

Methodology Applied
Scientific EffectReflection: Reflection

Data Source

PatentUS20250062304A1Semiconductor package and method of manufacturing the same
Publication Date: 2025.02.20 SAMSUNG ELECTRONICS CO LTD
  • US20250062304A1 patent drawing
  • US20250062304A1 patent drawing
  • US20250062304A1 patent drawing

AI summary

A semiconductor package includes a package substrate, a semiconductor chip disposed on an upper surface of the package substrate, and an EIC chip disposed on the package substrate and spaced apart from the semiconductor chip in a horizontal direction parallel to the upper surface of the package substrate. The semiconductor package further includes a PIC chip disposed on an upper surface of the EIC chip, wherein a horizontal surface area of the PIC chip is greater than a horizontal surface area of the EIC chip, and wherein a portion of PIC chip protrudes horizontally from the EIC chip. The semiconductor package further includes a reflective portion disposed on a lower surface of the portion of the PIC chip and spaced apart from the EIC chip in the horizontal direction, and an optical fiber connected to the reflective portion and spaced apart from the PIC chip in a vertical direction.