Semiconductor Package Layout With Flip-Chip and Option Bump Routing
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Solution Overview
Problem
There is a challenge in efficiently placing semiconductor chips within the limited area of a semiconductor package, as the size and number of chips increase, while maintaining improved electrical characteristics and low package height.
Innovation Solution
The semiconductor package includes a package substrate with a wiring structure, external connecting terminals, a first semiconductor chip flip-chip bonded on the substrate, a second semiconductor chip wire-bonded on the substrate, and specific pad and bump configurations to optimize chip placement and electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size and number of semiconductor chips are increased within the package, then the functional capability and electrical characteristics are improved, but the package area becomes insufficient and placement efficiency deteriorates
Solution Approach 1:
The patent transitions from conventional wire bonding to flip-chip bonding technology, fundamentally changing the dimensional approach of electrical connections. By bonding chips face-down with bumps penetrating through the substrate, the electrical connection path is shortened from a long wire route to a direct vertical path, improving electrical characteristics while reducing the horizontal space required for routing wires.
Solution Approach 2:
The package substrate serves multiple functions simultaneously: it provides mechanical support for the chips, establishes electrical connections through the wiring structure and external terminals, and enables thermal management. This multi-functionality allows efficient use of the limited package area by consolidating multiple system requirements into a single integrated substrate platform.
2Adaptability or versatility
If more semiconductor chips are placed in the package, then the functionality is enhanced, but the difficulty of efficient placement and space utilization increases
Solution Approach 1:
The package is divided into functionally independent modules: multiple semiconductor chips (including memory chips and logic chips), each with their own bump patterns and connection schemes, are placed on the substrate. The substrate itself is segmented into multiple wiring layers and external terminal regions, allowing independent optimization of each component's placement and connection without interfering with others.
Solution Approach 2:
The package substrate acts as an intermediary platform that coordinates the connections between multiple chips and external terminals. The wiring structure on the substrate mediates the electrical connections, routing signals between chip bumps and external pins, while the substrate's physical structure mediates the spatial arrangement, enabling efficient placement of multiple chips through standardized mounting interfaces.
3Ease of manufacture
If conventional wire bonding is used, then the manufacturing process is simple, but the package height increases and electrical characteristics deteriorate
Solution Approach 1:
The patent inverts the conventional bonding approach: instead of bonding chips face-up with wires extending upward from the chip surfaces, the chips are bonded face-down with bumps extending downward to contact the substrate. This inversion shortens the electrical path length, reduces package height, and improves signal integrity while maintaining manufacturing feasibility through established flip-chip bonding processes.
Data Source
AI summary
A semiconductor package includes a package substrate including a wiring structure, a plurality of external connecting terminals below the package substrate, a first semiconductor chip flip-chip bonded on and above the package substrate, a second semiconductor chip above the package substrate and horizontally spaced apart from the first semiconductor chip, and wire-bonded on the package substrate, a first power/ground pad on an upper face of the second semiconductor chip, an option pad on the package substrate and connected to the first power/ground pad by a wire, an option bump below the first semiconductor chip and connected to the option pad through the wiring structure, and a connecting bump below the first semiconductor chip and connected to a first external connecting terminal of the plurality of external connecting terminals, wherein the option bump is not electrically connected to any external connecting terminal of the plurality of external connecting terminals through only the wiring structure.