Semiconductor Package Test Region for Adhesive Overflow Detection
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Solution Overview
Problem
The thermal compression bonding process for stacking semiconductor chips results in non-conductive film flow, leading to exposed film portions outside the chips, which reduces product reliability and requires additional measurement processes, increasing time and cost.
Innovation Solution
A semiconductor package design that includes measurement structures on the test region of the first semiconductor chip, allowing for the measurement of exposed adhesive film portions between stacked chips, thereby enabling efficient sorting of defective products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thermal compression bonding process is used to stack chips, then chips can be stably bonded, but non-conductive film flows and disperses outside the chip, reducing product reliability
Solution Approach 1:
The chip surface is divided into a chip mounting region and a test region. The test region serves as a dedicated measurement area where exposed adhesive portions can be detected without affecting the bonding reliability of the chip mounting region.
Solution Approach 2:
Measurement structures are pre-formed on the test region before the bonding process. This allows for subsequent detection of exposed adhesive portions after bonding, enabling identification of unreliable products before final assembly.
2Reliability
If additional measurement process is added to measure exposed non-conductive film portions, then product reliability can be improved, but process time and process cost increase
Solution Approach 1:
The measurement structures are integrated into the chip substrate during the original chip manufacturing process. This merging of measurement functionality into the chip structure itself eliminates the need for separate, additional measurement processes, thereby reducing process time and cost while maintaining reliability assessment capability.
Solution Approach 2:
The chip structure itself provides the measurement capability through the integrated measurement structures on the test region. The chip self-contains the means for detecting exposed adhesive portions, eliminating the need for external measurement equipment and processes.
3Measurement precision
If measurement structures are added to the chip, then exposed adhesive portions can be measured, but chip structure complexity increases
Solution Approach 1:
The measurement structures are localized to the test region, which is a specific area on the chip surface. This local placement allows for measurement functionality without requiring the entire chip structure to be modified, thus minimizing the increase in overall chip complexity while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for accurate measurement and sorting of defective semiconductor packages, reducing process time and cost by eliminating the need for additional measurement processes.
Implementation Method 1
an adhesive layer filling a gap between the first semiconductor chip and the second semiconductor chip
Implementation Method 2
A plurality of chips may be sequentially stacked using an adhesive film by a thermal compression bonding (TCB) process. In the thermal compression bonding process, the adhesive film such as a non-conductive film may be used to stably bond conductive bumps for connection between the chips
Data Source
AI summary
A semiconductor package includes a first semiconductor chip having a chip mounting region on a central portion thereof and a test region surrounding the chip mounting region; a plurality of first measurement structures on the test region and sequentially arranged to be spaced apart from an edge of the chip mounting region; a second semiconductor chip mounted on the chip mounting region of the first semiconductor chip via a plurality of conductive bumps; an adhesive layer filling a gap between the first semiconductor chip and the second semiconductor chip, and including a central portion in the chip mounting region and at least one overflow portion protruding from the central portion to the test region to contact at least one of the plurality of first measurement structures; and a molding member on the upper surface of the first semiconductor chip to cover side surfaces of the second semiconductor chip.