3D Semiconductor Package With Partially Overlapping Chips

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Solution Overview

Problem

Current semiconductor packaging is limited by two-dimensional integration, which restricts the density of components on a chip area, and there is a need for three-dimensional packaging to enhance integration density.

Innovation Solution

A semiconductor package with a first device die attached to a package substrate and a second device die stacked over the first, both with electrical connectors that connect their active sides to the substrate, utilizing conductive pillars and solder joints for improved connectivity, and an encapsulant for lateral coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If two-dimensional integration is used to increase component density, then manufacturing complexity is reduced, but integration density is limited by physical constraints of the chip area

Engineering Contradiction:

Improveintegration densityVSAvoidpackaging structure complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by positioning device dies at different heights above the package substrate. Multiple dies are stacked in the z-direction with electrical connectors extending through intermediate layers, enabling higher integration density without increasing the footprint area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If electrical connectors are made longer to connect stacked dies to the package substrate, then connectivity is achieved, but resistivity and impedance increase particularly under high-frequency conditions

Engineering Contradiction:

Improveelectrical connection qualityVSAvoidresistivity and impedance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces intermediate distribution layers (redistribution layers) positioned between the stacked device dies and the package substrate. These intermediary layers provide multiple connection points and shorter electrical pathways, reducing the overall length of electrical connectors and thereby decreasing resistivity and impedance while maintaining reliable electrical connectivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Area of stationary object

If three-dimensional stacking is implemented to enhance integration density, then space utilization is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvespace utilizationVSAvoidalignment precision

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent incorporates alignment marks and positioning structures on the package substrate and device dies before the stacking process. These pre-established reference features enable precise alignment during the assembly of multiple dies in the vertical direction, ensuring accurate registration of electrical connectors and conductive patterns without requiring ultra-precise positioning during assembly.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the resistivity and impedance of electrical connectors, enhancing the electrical connection between the die stack and the package substrate, particularly under high-frequency conditions, and allows for a more efficient use of space in semiconductor packaging.

Implementation Method 1

first electrical connectors, connecting the active side of the first device die to the package substrate; second electrical connectors, connecting the portion of the active side of the second device die to the package substrate

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

the first electrical connectors respectively comprise a first conductive pillar and a first solder joint connecting the first conductive pillar to the package substrate, and the second electrical connectors respectively comprise a second conductive pillar and a second solder joint connecting the second conductive pillar to the package substrate

Methodology Applied

Scientific EffectSoldering: Soldering

Implementation Method 3

a first adhesive material, disposed between the first device die and the package substrate; and a second adhesive material, disposed between the first device die and the second device die

Methodology Applied

Scientific EffectAdhesion: Adhesive

Data Source

PatentUS11227814B2Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof

Publication Date: 2022.01.18 NAN YA TECH

AI summary

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.