Semiconductor Package Pad Region Layout for Cost Reduction

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Solution Overview

Problem

Conventional semiconductor packages face challenges in reducing costs and minimizing complexity due to the need for individual designs for various customer demands, with increased costs and complexity when multiple ICs are mounted, and decreased antenna characteristics when wireless modules are stacked.

Innovation Solution

A semiconductor package design featuring a substrate with multiple pad regions, where the second pad region surrounds the first pad region in at least three rows, allowing for shared substrate usage and adaptable mounting configurations, including the option to mount or omit the BBIC, to reduce costs and enhance versatility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional semiconductor package design is used with individual designs for various customer demands, then the package can meet specific customer requirements, but the cost increases and complexity increases when multiple ICs are mounted

Engineering Contradiction:
Improveadaptability to customer demandsVSAvoidpackage complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The substrate is designed with multiple pad regions (first pad region, second pad region, third pad region) that can accommodate different IC mounting configurations. The same substrate can be used whether one IC or multiple ICs are mounted, eliminating the need for different substrate designs for different customer requirements. This universal design reduces both cost and complexity while maintaining adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The substrate is divided into multiple functional pad regions: a first pad region for mounting a first IC, a second pad region for mounting a second IC, and a third pad region for mounting a third IC. This segmentation allows flexible configuration where different combinations of ICs can be mounted on the same substrate type, enabling customisation without requiring different substrate designs.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple ICs are mounted in a semiconductor package, then more functions are integrated, but the cost increases

Engineering Contradiction:
Improvenumber of ICs mountedVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

A single substrate design with multiple pad regions serves multiple purposes: it can mount one IC or multiple ICs depending on customer requirements. This universal substrate eliminates the need to manufacture different substrate types for different IC configurations, reducing manufacturing costs while maintaining the flexibility to accommodate varying numbers of ICs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Volume of moving object

If wireless modules are stacked vertically, then space is reduced, but antenna characteristics deteriorate

Engineering Contradiction:
Improvepackage sizeVSAvoidantenna characteristics
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

Instead of stacking wireless modules vertically in the thickness direction, the patent arranges multiple ICs and their associated wireless modules horizontally on the same substrate plane. This lateral arrangement maintains better antenna characteristics by avoiding interference from stacked modules while still achieving compact packaging through efficient use of the substrate area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9293419B2Semiconductor package and semiconductor device
Publication Date: 2016.03.22 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US9293419B2 patent drawing
  • US9293419B2 patent drawing
  • US9293419B2 patent drawing

AI summary

A semiconductor package includes a first substrate including a first surface layer where a first pad region and a second pad region are formed, the first pad region including a plurality of first pads for connection to a first IC, the second pad region including a plurality of second pads for connection to a second substrate, and a second surface layer where a third pad region including a plurality of third pads for connection to a second IC is formed, the second surface layer being formed on an opposite side of the first surface layer. The second pads surround the first pad region in at least three rows, and one or more pads included in the second pads and arranged in an inner portion are connected to one or more pads included in the first pads and to one or more pads included in the third pads.