Semiconductor Package Pad Segmentation for Signal Speed
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently transmitting signals and data between multiple semiconductor chips due to high loading on pads, which can slow down operating speed and complicate electrical connections.
Innovation Solution
A semiconductor package design that includes a substrate with multiple semiconductor chips stacked and electrically connected through specific pad configurations, where the first pad connects the second semiconductor chip to the integrated circuit section, and the second pad connects the third semiconductor chip, with the third pad acting as a transmission path for signals between all chips, reducing the number of chips connected to each pad and shortening electrical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple semiconductor chips are connected to the same pad, then the device complexity is reduced, but the operating speed decreases due to high loading
Solution Approach 1:
The pad connections are segmented by creating distinct connection groups: first pads connect only to second semiconductor chips, second pads connect only to third semiconductor chips, and third pads connect to both second and third semiconductor chips. This segmentation reduces the loading on each pad type, thereby improving operating speed while maintaining manageable device complexity through organized connection groups.
2Quantity of substance
If the electrical path between chips is lengthened to accommodate more connections, then more chips can be integrated, but the signal transmission efficiency decreases
Solution Approach 1:
The patent transitions from a planar connection layout to a three-dimensional stacked configuration where second and third semiconductor chips are vertically stacked. This dimensional change allows multiple chips to be integrated without significantly increasing the electrical path length, as connections occur through vertical stacking rather than horizontal routing, thereby maintaining signal transmission efficiency while increasing chip integration density.
Data Source
AI summary
A semiconductor package including a substrate including an external terminal; a first semiconductor chip on the substrate and having a first and a second region; at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and at least one third semiconductor chip on the at least one second semiconductor chip, wherein the first semiconductor chip includes a first pad electrically connected to the at least one second semiconductor chip; a second pad electrically connected to the at least one third semiconductor chip; and a third pad electrically connected to the external terminal, the first pad is on the top surface of the first region, and at least one of the second pad and the third pad is on a top surface of the second region.