Semiconductor Package Substrate Pad Segmentation for Fine Pitch
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Solution Overview
Problem
In semiconductor package substrates, the electrically connecting pads are not completely covered by semiconductor chip bumps, leading to stress concentration and poor bonding, and the pitch distance between pads is not suitable for fine pitch applications due to extending circuits.
Innovation Solution
A semiconductor package substrate with a dielectric layer and conductive vias exposing first electrically connecting pads without extending circuits, an adhesive layer made of immersion or printed tin for complete coverage by chip bumps, and a second circuit layer for increased layout density and bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrically connecting pads extend sideward to circuits, then circuits can be electrically connected to pads, but bumps cannot completely cover the pads leading to stress concentration and poor bonding
Solution Approach 1:
The pad structure is segmented into two distinct parts: the electrically connecting pad that extends to the circuit for electrical connection, and the mounting pad that remains separate and exposed for complete bump coverage. This segmentation allows each part to fulfill its specific function without compromising the other, resolving the contradiction between electrical connection and complete pad coverage.
Solution Approach 2:
A separate mounting pad is introduced as an intermediary element between the electrically connecting pad and the bump. The mounting pad serves as a dedicated platform for bump mounting, ensuring complete coverage and proper stress distribution, while the electrically connecting pad handles the electrical connection function independently.
2Reliability
If circuits are formed between adjacent electrically connecting pads, then electrical connectivity is achieved, but the distance between pads increases preventing fine pitch application
Solution Approach 1:
The electrical connection function is segmented between two separate structures: the electrically connecting pad that provides vertical connection to the circuit through the dielectric layer, and the circuit trace that provides horizontal connection. This segmentation allows pads to be placed closer together while maintaining electrical connectivity through the vertical via structure, enabling fine pitch applications.
Solution Approach 2:
The electrical connection is moved from a purely horizontal plane to a three-dimensional structure by forming pads through the dielectric layer in the vertical dimension. This allows adjacent pads to be positioned closer in the horizontal plane while maintaining electrical connectivity through the vertical via, thereby reducing pad pitch distance for fine pitch applications.
3Ease of manufacture
If opening aperture is large to expose multiple pads and accommodate underfill, then underfill application is facilitated, but flash incidence may occur
Solution Approach 1:
The opening is segmented into multiple smaller individual openings, each exposing a single mounting pad. This segmentation reduces the aperture size of each opening, minimizing flash incidence risk while still allowing underfill to flow through and accommodate the bump and mounting pad structure. The distributed smaller openings maintain ease of manufacture benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances bonding strength between semiconductor chips and the substrate, allowing for finer pitch applications by ensuring complete coverage of pads and reducing stress concentration.
Implementation Method 1
allowing the bumps and the adhesive layer to fuse together
Implementation Method 2
an adhesive layer formed on the first electrically connecting pads
Data Source
AI summary
A semiconductor package substrate includes a main body with a surface having a first circuit layer thereon and a dielectric layer covering the first circuit layer, with a plurality of vias on a portion of the first circuit layer; a plurality of first conductive vias disposed in the vias; a plurality of first electrically connecting pads on the first conductive vias and completely exposed on the dielectric layer having no extending circuits for a semiconductor chip to be mounted thereon, the first electrically connecting pad being electrically connected to the first circuit layer of the first conductive via; and an insulating protective layer disposed on the main body with an opening for completely exposing the first electrically connecting pads, whereby the circuit layout density is increased without disposing circuits between the electrically connecting pads.


