Semiconductor Package Wiring Structure for High-Yield Panel Packaging
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Solution Overview
Problem
The existing semiconductor packaging technology faces high costs due to low wafer utilization and high yield loss from cracking or distortion during the sequential formation of wiring layers, which occupies a large area and reduces the production capacity.
Innovation Solution
The proposed solution involves forming semiconductor packages using a panel-level process with a larger substrate, where at least two wiring layers are created with varying precision, and the semiconductor elements are disposed on these layers, reducing the need for wafer-level processing and improving yield and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wafer-level packaging technology is employed to achieve high precision and small size, then manufacturing precision and product size are improved, but production cost increases and productivity decreases
Solution Approach 1:
The patent segments the packaging process into two distinct stages: wafer-level packaging for high-precision bonding of semiconductor elements to wiring layers, and panel-level packaging for mass production of multiple packages simultaneously. This segmentation allows each stage to optimize for its specific function, resolving the contradiction between precision and productivity.
Solution Approach 2:
The patent transitions from traditional two-dimensional wafer processing to three-dimensional stacked packaging with multiple wiring layers (first wiring layer, second wiring layer, etc.) connected through through-holes. This dimensional change enables higher integration and productivity without sacrificing bonding precision.
2Manufacturing precision
If sequential formation of wiring layers is performed at wafer-level to ensure high precision, then manufacturing precision is improved, but yield loss increases due to cracking or distortion
Solution Approach 1:
The patent performs preliminary bonding of semiconductor elements to the first wiring layer at wafer-level with high precision before proceeding to subsequent packaging steps. This preliminary action ensures precise electrical connections are established early, while later panel-level processing handles the formation of additional wiring layers with reduced risk of distortion.
Solution Approach 2:
The patent designs the packaging structure with multiple wiring layers and encapsulation that provide mechanical support and stress distribution, cushioning against cracking or distortion that might occur during subsequent processing steps. The encapsulation layer protects the bonded interfaces from mechanical stress.
3Manufacturing precision
If wafer-level processing is used to achieve high precision packaging, then manufacturing precision is improved, but material cost increases due to low wafer utilization
Solution Approach 1:
The patent merges multiple packaging operations into a unified panel-level process after the initial wafer-level bonding. Multiple semiconductor elements and wiring layers are combined and packaged together in batches, increasing material utilization efficiency and reducing per-unit costs while maintaining the precision benefits of wafer-level bonding.
Solution Approach 2:
The patent changes the scale parameter from individual wafer processing to panel-level batch processing. By processing multiple packages simultaneously at the panel level, material utilization improves and costs decrease, while the critical bonding precision is maintained through the initial wafer-level process.
4Area of moving object
If fan-out wafer-level packaging is employed to achieve small size and high pin count, then product size and functionality are improved, but production cost increases
Solution Approach 1:
The patent implements a nested multi-layer wiring structure where first wiring layers, second wiring layers, and encapsulation layers are stacked and interconnected through through-holes. This nested arrangement achieves high pin count and functionality within a compact footprint while enabling batch processing that reduces manufacturing costs.
Solution Approach 2:
The patent creates a universal panel-level packaging platform that can accommodate multiple semiconductor elements and wiring layer configurations simultaneously. This multi-functional approach increases production efficiency and reduces per-unit costs while maintaining the small size benefits of wafer-level packaging.
Data Source
AI summary
A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.